drivers/crypto/ccp/ccp-dev.h
Source file repositories/reference/linux-study-clean/drivers/crypto/ccp/ccp-dev.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/ccp/ccp-dev.h- Extension
.h- Size
- 16429 bytes
- Lines
- 674
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/spinlock.hlinux/mutex.hlinux/list.hlinux/wait.hlinux/dma-direction.hlinux/dmapool.hlinux/hw_random.hlinux/bitops.hlinux/interrupt.hlinux/irqreturn.hlinux/dmaengine.hsp-dev.h
Detected Declarations
struct ccp_opstruct ccp_devicestruct ccp_cmdstruct ccp_fnsstruct ccp_dma_cmdstruct ccp_dma_descstruct ccp_dma_chanstruct ccp_cmd_queuestruct ccp_devicestruct ccp_dma_infostruct ccp_dm_workareastruct ccp_sg_workareastruct ccp_datastruct ccp_memstruct ccp_aes_opstruct ccp_xts_aes_opstruct ccp_des3_opstruct ccp_sha_opstruct ccp_rsa_opstruct ccp_passthru_opstruct ccp_ecc_opstruct ccp_opstruct dword0struct dword3struct dword7struct ccp5_descstruct ccp_actionsenum ccp_memtypefunction ccp_addr_lofunction ccp_addr_hi
Annotated Snippet
struct ccp_dma_cmd {
struct list_head entry;
struct ccp_cmd ccp_cmd;
};
struct ccp_dma_desc {
struct list_head entry;
struct ccp_device *ccp;
struct list_head pending;
struct list_head active;
enum dma_status status;
struct dma_async_tx_descriptor tx_desc;
size_t len;
};
struct ccp_dma_chan {
struct ccp_device *ccp;
spinlock_t lock;
struct list_head created;
struct list_head pending;
struct list_head active;
struct list_head complete;
struct tasklet_struct cleanup_tasklet;
enum dma_status status;
struct dma_chan dma_chan;
};
struct ccp_cmd_queue {
struct ccp_device *ccp;
/* Queue identifier */
u32 id;
/* Queue dma pool */
struct dma_pool *dma_pool;
/* Queue base address (not neccessarily aligned)*/
struct ccp5_desc *qbase;
/* Aligned queue start address (per requirement) */
struct mutex q_mutex ____cacheline_aligned;
unsigned int qidx;
/* Version 5 has different requirements for queue memory */
unsigned int qsize;
dma_addr_t qbase_dma;
dma_addr_t qdma_tail;
/* Per-queue reserved storage block(s) */
u32 sb_key;
u32 sb_ctx;
/* Bitmap of LSBs that can be accessed by this queue */
DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
/* Private LSB that is assigned to this queue, or -1 if none.
* Bitmap for my private LSB, unused otherwise
*/
int lsb;
DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
/* Queue processing thread */
struct task_struct *kthread;
unsigned int active;
unsigned int suspended;
/* Number of free command slots available */
unsigned int free_slots;
/* Interrupt masks */
u32 int_ok;
u32 int_err;
/* Register addresses for queue */
void __iomem *reg_control;
void __iomem *reg_tail_lo;
void __iomem *reg_head_lo;
void __iomem *reg_int_enable;
void __iomem *reg_interrupt_status;
void __iomem *reg_status;
void __iomem *reg_int_status;
void __iomem *reg_dma_status;
void __iomem *reg_dma_read_status;
void __iomem *reg_dma_write_status;
Annotation
- Immediate include surface: `linux/device.h`, `linux/spinlock.h`, `linux/mutex.h`, `linux/list.h`, `linux/wait.h`, `linux/dma-direction.h`, `linux/dmapool.h`, `linux/hw_random.h`.
- Detected declarations: `struct ccp_op`, `struct ccp_device`, `struct ccp_cmd`, `struct ccp_fns`, `struct ccp_dma_cmd`, `struct ccp_dma_desc`, `struct ccp_dma_chan`, `struct ccp_cmd_queue`, `struct ccp_device`, `struct ccp_dma_info`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.