drivers/crypto/chelsio/chcr_algo.c
Source file repositories/reference/linux-study-clean/drivers/crypto/chelsio/chcr_algo.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/chelsio/chcr_algo.c- Extension
.c- Size
- 126643 bytes
- Lines
- 4402
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/crypto.hlinux/skbuff.hlinux/rtnetlink.hlinux/highmem.hlinux/scatterlist.hcrypto/aes.hcrypto/algapi.hcrypto/gcm.hcrypto/sha1.hcrypto/sha2.hcrypto/authenc.hcrypto/ctr.hcrypto/gf128mul.hcrypto/internal/aead.hcrypto/null.hcrypto/internal/skcipher.hcrypto/aead.hcrypto/scatterwalk.hcrypto/internal/hash.ht4fw_api.ht4_msg.hchcr_core.hchcr_algo.hchcr_crypto.h
Detected Declarations
function chcr_init_hctx_per_wrfunction sg_nents_xlenfunction get_aead_subtypefunction chcr_verify_tagfunction chcr_inc_wrcountfunction chcr_dec_wrcountfunction chcr_handle_aead_respfunction get_aes_decrypt_keyfunction chcr_prepare_hmac_keyfunction is_hmacfunction dsgl_walk_initfunction dsgl_walk_endfunction dsgl_walk_add_pagefunction dsgl_walk_add_sgfunction ulptx_walk_initfunction ulptx_walk_endfunction ulptx_walk_add_pagefunction ulptx_walk_add_sgfunction get_cryptoalg_subtypefunction cxgb4_is_crypto_q_fullfunction generate_copy_rrkeyfunction chcr_hash_ent_in_wrfunction chcr_sg_ent_in_wrfunction chcr_cipher_fallbackfunction get_qidxsfunction create_wreqfunction chcr_keyctx_ck_sizefunction chcr_cipher_fallback_setkeyfunction chcr_aes_cbc_setkeyfunction chcr_aes_ctr_setkeyfunction chcr_aes_rfc3686_setkeyfunction ctr_add_ivfunction adjust_ctr_overflowfunction chcr_update_tweakfunction chcr_update_cipher_ivfunction chcr_final_cipher_ivfunction chcr_handle_cipher_respfunction process_cipherfunction chcr_aes_encryptfunction chcr_aes_decryptfunction chcr_device_initfunction chcr_init_tfmfunction chcr_rfc3686_initfunction chcr_exit_tfmfunction get_alg_configfunction chcr_ahash_updatefunction create_last_hash_blockfunction chcr_ahash_final
Annotated Snippet
if (sg_dma_len(sg) <= skip) {
skip -= sg_dma_len(sg);
skip_len = 0;
sg = sg_next(sg);
} else {
skip_len = skip;
skip = 0;
}
}
while (sg && reqlen) {
less = min(reqlen, sg_dma_len(sg) - skip_len);
nents += DIV_ROUND_UP(less, entlen);
reqlen -= less;
skip_len = 0;
sg = sg_next(sg);
}
return nents;
}
static inline int get_aead_subtype(struct crypto_aead *aead)
{
struct aead_alg *alg = crypto_aead_alg(aead);
struct chcr_alg_template *chcr_crypto_alg =
container_of(alg, struct chcr_alg_template, alg.aead);
return chcr_crypto_alg->type & CRYPTO_ALG_SUB_TYPE_MASK;
}
void chcr_verify_tag(struct aead_request *req, u8 *input, int *err)
{
u8 temp[SHA512_DIGEST_SIZE];
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
int authsize = crypto_aead_authsize(tfm);
struct cpl_fw6_pld *fw6_pld;
int cmp = 0;
fw6_pld = (struct cpl_fw6_pld *)input;
if ((get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106) ||
(get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_GCM)) {
cmp = crypto_memneq(&fw6_pld->data[2], (fw6_pld + 1), authsize);
} else {
sg_pcopy_to_buffer(req->src, sg_nents(req->src), temp,
authsize, req->assoclen +
req->cryptlen - authsize);
cmp = crypto_memneq(temp, (fw6_pld + 1), authsize);
}
if (cmp)
*err = -EBADMSG;
else
*err = 0;
}
static int chcr_inc_wrcount(struct chcr_dev *dev)
{
if (dev->state == CHCR_DETACH)
return 1;
atomic_inc(&dev->inflight);
return 0;
}
static inline void chcr_dec_wrcount(struct chcr_dev *dev)
{
atomic_dec(&dev->inflight);
}
static inline int chcr_handle_aead_resp(struct aead_request *req,
unsigned char *input,
int err)
{
struct chcr_aead_reqctx *reqctx = aead_request_ctx_dma(req);
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
struct chcr_dev *dev = a_ctx(tfm)->dev;
chcr_aead_common_exit(req);
if (reqctx->verify == VERIFY_SW) {
chcr_verify_tag(req, input, &err);
reqctx->verify = VERIFY_HW;
}
chcr_dec_wrcount(dev);
aead_request_complete(req, err);
return err;
}
static void get_aes_decrypt_key(unsigned char *dec_key,
const unsigned char *key,
unsigned int keylength)
{
u32 temp;
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/crypto.h`, `linux/skbuff.h`, `linux/rtnetlink.h`, `linux/highmem.h`, `linux/scatterlist.h`, `crypto/aes.h`.
- Detected declarations: `function chcr_init_hctx_per_wr`, `function sg_nents_xlen`, `function get_aead_subtype`, `function chcr_verify_tag`, `function chcr_inc_wrcount`, `function chcr_dec_wrcount`, `function chcr_handle_aead_resp`, `function get_aes_decrypt_key`, `function chcr_prepare_hmac_key`, `function is_hmac`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.