drivers/crypto/inside-secure/eip93/eip93-hash.c
Source file repositories/reference/linux-study-clean/drivers/crypto/inside-secure/eip93/eip93-hash.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/inside-secure/eip93/eip93-hash.c- Extension
.c- Size
- 24886 bytes
- Lines
- 876
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/sha1.hcrypto/sha2.hcrypto/md5.hcrypto/hmac.hlinux/dma-mapping.hlinux/delay.heip93-cipher.heip93-hash.heip93-main.heip93-common.heip93-regs.h
Detected Declarations
function Copyrightfunction list_for_each_entry_safefunction eip93_hash_free_sa_recordfunction eip93_hash_handle_resultfunction eip93_hash_init_sa_state_digestfunction eip93_hash_export_sa_statefunction __eip93_hash_initfunction eip93_send_hash_reqfunction eip93_hash_initfunction finalfunction eip93_hash_updatefunction finupfunction eip93_hash_finalfunction eip93_hash_finupfunction eip93_hash_hmac_setkeyfunction eip93_hash_cra_initfunction eip93_hash_digestfunction eip93_hash_importfunction eip93_hash_export
Annotated Snippet
if (!IS_HASH_MD5(ctx->flags)) {
for (i = 0; i < digestsize / sizeof(u32); i++) {
u32 *digest = (u32 *)sa_state->state_i_digest;
digest[i] = be32_to_cpu((__be32 __force)digest[i]);
}
}
memcpy(req->result, sa_state->state_i_digest, digestsize);
}
eip93_hash_free_sa_record(req);
eip93_hash_free_data_blocks(req);
ahash_request_complete(req, err);
}
static void eip93_hash_init_sa_state_digest(u32 hash, u8 *digest)
{
static const u32 sha256_init[] = {
SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
};
static const u32 sha224_init[] = {
SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7
};
static const u32 sha1_init[] = {
SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4
};
static const u32 md5_init[] = {
MD5_H0, MD5_H1, MD5_H2, MD5_H3
};
/* Init HASH constant */
switch (hash) {
case EIP93_HASH_SHA256:
memcpy(digest, sha256_init, sizeof(sha256_init));
return;
case EIP93_HASH_SHA224:
memcpy(digest, sha224_init, sizeof(sha224_init));
return;
case EIP93_HASH_SHA1:
memcpy(digest, sha1_init, sizeof(sha1_init));
return;
case EIP93_HASH_MD5:
memcpy(digest, md5_init, sizeof(md5_init));
return;
default: /* Impossible */
return;
}
}
static void eip93_hash_export_sa_state(struct ahash_request *req,
struct eip93_hash_export_state *state)
{
struct eip93_hash_reqctx *rctx = ahash_request_ctx_dma(req);
struct sa_state *sa_state = &rctx->sa_state;
/*
* EIP93 have special handling for state_byte_cnt in sa_state.
* Even if a zero packet is passed (and a BADMSG is returned),
* state_byte_cnt is incremented to the digest handled (with the hash
* primitive). This is problematic with export/import as EIP93
* expect 0 state_byte_cnt for the very first iteration.
*/
if (!rctx->len)
memset(state->state_len, 0, sizeof(u32) * 2);
else
memcpy(state->state_len, sa_state->state_byte_cnt,
sizeof(u32) * 2);
memcpy(state->state_hash, sa_state->state_i_digest,
SHA256_DIGEST_SIZE);
state->len = rctx->len;
state->data_used = rctx->data_used;
}
static void __eip93_hash_init(struct ahash_request *req)
{
struct eip93_hash_reqctx *rctx = ahash_request_ctx_dma(req);
struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
struct eip93_hash_ctx *ctx = crypto_ahash_ctx(ahash);
struct sa_record *sa_record = &rctx->sa_record;
int digestsize;
digestsize = crypto_ahash_digestsize(ahash);
eip93_set_sa_record(sa_record, 0, ctx->flags);
sa_record->sa_cmd0_word |= EIP93_SA_CMD_HASH_FROM_STATE;
sa_record->sa_cmd0_word |= EIP93_SA_CMD_SAVE_HASH;
Annotation
- Immediate include surface: `crypto/sha1.h`, `crypto/sha2.h`, `crypto/md5.h`, `crypto/hmac.h`, `linux/dma-mapping.h`, `linux/delay.h`, `eip93-cipher.h`, `eip93-hash.h`.
- Detected declarations: `function Copyright`, `function list_for_each_entry_safe`, `function eip93_hash_free_sa_record`, `function eip93_hash_handle_result`, `function eip93_hash_init_sa_state_digest`, `function eip93_hash_export_sa_state`, `function __eip93_hash_init`, `function eip93_send_hash_req`, `function eip93_hash_init`, `function final`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.