drivers/crypto/inside-secure/safexcel_cipher.c
Source file repositories/reference/linux-study-clean/drivers/crypto/inside-secure/safexcel_cipher.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/inside-secure/safexcel_cipher.c- Extension
.c- Size
- 110380 bytes
- Lines
- 3759
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/unaligned.hlinux/device.hlinux/dma-mapping.hlinux/dmapool.hcrypto/aead.hcrypto/aes.hcrypto/authenc.hcrypto/chacha.hcrypto/ctr.hcrypto/internal/des.hcrypto/gcm.hcrypto/ghash.hcrypto/md5.hcrypto/poly1305.hcrypto/sha1.hcrypto/sha2.hcrypto/sm3.hcrypto/sm4.hcrypto/xts.hcrypto/skcipher.hcrypto/internal/aead.hcrypto/internal/skcipher.hsafexcel.h
Detected Declarations
struct safexcel_cipher_ctxstruct safexcel_cipher_reqenum safexcel_cipher_directionenum safexcel_cipher_algfunction safexcel_skcipher_ivfunction safexcel_skcipher_tokenfunction safexcel_aead_ivfunction safexcel_aead_tokenfunction safexcel_skcipher_aes_setkeyfunction safexcel_aead_setkeyfunction safexcel_context_controlfunction safexcel_handle_req_resultfunction safexcel_send_reqfunction safexcel_handle_inv_resultfunction safexcel_skcipher_handle_resultfunction safexcel_aead_handle_resultfunction safexcel_cipher_send_invfunction safexcel_skcipher_sendfunction safexcel_aead_sendfunction safexcel_cipher_exit_invfunction safexcel_skcipher_exit_invfunction safexcel_aead_exit_invfunction safexcel_queue_reqfunction safexcel_encryptfunction safexcel_decryptfunction safexcel_skcipher_cra_initfunction safexcel_cipher_cra_exitfunction safexcel_skcipher_cra_exitfunction safexcel_aead_cra_exitfunction safexcel_skcipher_aes_ecb_cra_initfunction safexcel_skcipher_aes_cbc_cra_initfunction safexcel_skcipher_aesctr_setkeyfunction safexcel_skcipher_aes_ctr_cra_initfunction safexcel_des_setkeyfunction safexcel_skcipher_des_cbc_cra_initfunction safexcel_skcipher_des_ecb_cra_initfunction safexcel_des3_ede_setkeyfunction safexcel_skcipher_des3_cbc_cra_initfunction safexcel_skcipher_des3_ecb_cra_initfunction safexcel_aead_encryptfunction safexcel_aead_decryptfunction safexcel_aead_cra_initfunction safexcel_aead_md5_cra_initfunction safexcel_aead_sha1_cra_initfunction safexcel_aead_sha256_cra_initfunction safexcel_aead_sha224_cra_initfunction safexcel_aead_sha512_cra_initfunction safexcel_aead_sha384_cra_init
Annotated Snippet
struct safexcel_cipher_ctx {
struct safexcel_context base;
struct safexcel_crypto_priv *priv;
u32 mode;
enum safexcel_cipher_alg alg;
u8 aead; /* !=0=AEAD, 2=IPSec ESP AEAD, 3=IPsec ESP GMAC */
u8 xcm; /* 0=authenc, 1=GCM, 2 reserved for CCM */
u8 aadskip;
u8 blocksz;
u32 ivmask;
u32 ctrinit;
__le32 key[16];
u32 nonce;
unsigned int key_len, xts;
/* All the below is AEAD specific */
u32 hash_alg;
u32 state_sz;
struct crypto_aead *fback;
};
struct safexcel_cipher_req {
enum safexcel_cipher_direction direction;
/* Number of result descriptors associated to the request */
unsigned int rdescs;
bool needs_inv;
int nr_src, nr_dst;
};
static int safexcel_skcipher_iv(struct safexcel_cipher_ctx *ctx, u8 *iv,
struct safexcel_command_desc *cdesc)
{
if (ctx->mode == CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD) {
cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD;
/* 32 bit nonce */
cdesc->control_data.token[0] = ctx->nonce;
/* 64 bit IV part */
memcpy(&cdesc->control_data.token[1], iv, 8);
/* 32 bit counter, start at 0 or 1 (big endian!) */
cdesc->control_data.token[3] =
(__force u32)cpu_to_be32(ctx->ctrinit);
return 4;
}
if (ctx->alg == SAFEXCEL_CHACHA20) {
cdesc->control_data.options |= EIP197_OPTION_4_TOKEN_IV_CMD;
/* 96 bit nonce part */
memcpy(&cdesc->control_data.token[0], &iv[4], 12);
/* 32 bit counter */
cdesc->control_data.token[3] = *(u32 *)iv;
return 4;
}
cdesc->control_data.options |= ctx->ivmask;
memcpy(cdesc->control_data.token, iv, ctx->blocksz);
return ctx->blocksz / sizeof(u32);
}
static void safexcel_skcipher_token(struct safexcel_cipher_ctx *ctx, u8 *iv,
struct safexcel_command_desc *cdesc,
struct safexcel_token *atoken,
u32 length)
{
struct safexcel_token *token;
int ivlen;
ivlen = safexcel_skcipher_iv(ctx, iv, cdesc);
if (ivlen == 4) {
/* No space in cdesc, instruction moves to atoken */
cdesc->additional_cdata_size = 1;
token = atoken;
} else {
/* Everything fits in cdesc */
token = (struct safexcel_token *)(cdesc->control_data.token + 2);
/* Need to pad with NOP */
eip197_noop_token(&token[1]);
}
token->opcode = EIP197_TOKEN_OPCODE_DIRECTION;
token->packet_length = length;
token->stat = EIP197_TOKEN_STAT_LAST_PACKET |
EIP197_TOKEN_STAT_LAST_HASH;
token->instructions = EIP197_TOKEN_INS_LAST |
EIP197_TOKEN_INS_TYPE_CRYPTO |
EIP197_TOKEN_INS_TYPE_OUTPUT;
}
static void safexcel_aead_iv(struct safexcel_cipher_ctx *ctx, u8 *iv,
Annotation
- Immediate include surface: `linux/unaligned.h`, `linux/device.h`, `linux/dma-mapping.h`, `linux/dmapool.h`, `crypto/aead.h`, `crypto/aes.h`, `crypto/authenc.h`, `crypto/chacha.h`.
- Detected declarations: `struct safexcel_cipher_ctx`, `struct safexcel_cipher_req`, `enum safexcel_cipher_direction`, `enum safexcel_cipher_alg`, `function safexcel_skcipher_iv`, `function safexcel_skcipher_token`, `function safexcel_aead_iv`, `function safexcel_aead_token`, `function safexcel_skcipher_aes_setkey`, `function safexcel_aead_setkey`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.