drivers/crypto/inside-secure/safexcel_hash.c
Source file repositories/reference/linux-study-clean/drivers/crypto/inside-secure/safexcel_hash.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/inside-secure/safexcel_hash.c- Extension
.c- Size
- 85999 bytes
- Lines
- 3013
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/aes.hcrypto/hmac.hcrypto/md5.hcrypto/sha1.hcrypto/sha2.hcrypto/sha3.hcrypto/skcipher.hcrypto/sm3.hcrypto/internal/cipher.hlinux/device.hlinux/dma-mapping.hlinux/dmapool.hsafexcel.h
Detected Declarations
struct safexcel_ahash_ctxstruct safexcel_ahash_reqfunction safexcel_queued_lenfunction safexcel_hash_tokenfunction safexcel_context_controlfunction safexcel_handle_req_resultfunction safexcel_ahash_send_reqfunction for_each_sgfunction safexcel_handle_inv_resultfunction safexcel_handle_resultfunction safexcel_ahash_send_invfunction safexcel_ahash_sendfunction safexcel_ahash_exit_invfunction safexcel_ahash_cachefunction safexcel_ahash_enqueuefunction safexcel_ahash_updatefunction safexcel_ahash_finalfunction safexcel_ahash_finupfunction safexcel_ahash_exportfunction safexcel_ahash_importfunction safexcel_ahash_cra_initfunction safexcel_sha1_initfunction safexcel_sha1_digestfunction safexcel_ahash_cra_exitfunction safexcel_hmac_sha1_initfunction safexcel_hmac_sha1_digestfunction safexcel_hmac_init_padfunction safexcel_hmac_init_ivfunction __safexcel_hmac_setkeyfunction safexcel_hmac_setkeyfunction safexcel_hmac_alg_setkeyfunction safexcel_hmac_sha1_setkeyfunction safexcel_sha256_initfunction safexcel_sha256_digestfunction safexcel_sha224_initfunction safexcel_sha224_digestfunction safexcel_hmac_sha224_setkeyfunction safexcel_hmac_sha224_initfunction safexcel_hmac_sha224_digestfunction safexcel_hmac_sha256_setkeyfunction safexcel_hmac_sha256_initfunction safexcel_hmac_sha256_digestfunction safexcel_sha512_initfunction safexcel_sha512_digestfunction safexcel_sha384_initfunction safexcel_sha384_digestfunction safexcel_hmac_sha512_setkeyfunction safexcel_hmac_sha512_init
Annotated Snippet
struct safexcel_ahash_ctx {
struct safexcel_context base;
u32 alg;
u8 key_sz;
bool cbcmac;
bool do_fallback;
bool fb_init_done;
bool fb_do_setkey;
struct aes_enckey *aes;
struct crypto_ahash *fback;
struct crypto_shash *shpre;
struct shash_desc *shdesc;
};
struct safexcel_ahash_req {
bool last_req;
bool finish;
bool hmac;
bool needs_inv;
bool hmac_zlen;
bool len_is_le;
bool not_first;
bool xcbcmac;
int nents;
dma_addr_t result_dma;
u32 digest;
u8 state_sz; /* expected state size, only set once */
u8 block_sz; /* block size, only set once */
u8 digest_sz; /* output digest size, only set once */
__le32 state[SHA3_512_BLOCK_SIZE /
sizeof(__le32)] __aligned(sizeof(__le32));
u64 len;
u64 processed;
u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
dma_addr_t cache_dma;
unsigned int cache_sz;
u8 cache_next[HASH_CACHE_SIZE] __aligned(sizeof(u32));
};
static inline u64 safexcel_queued_len(struct safexcel_ahash_req *req)
{
return req->len - req->processed;
}
static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
u32 input_length, u32 result_length,
bool cbcmac)
{
struct safexcel_token *token =
(struct safexcel_token *)cdesc->control_data.token;
token[0].opcode = EIP197_TOKEN_OPCODE_DIRECTION;
token[0].packet_length = input_length;
token[0].instructions = EIP197_TOKEN_INS_TYPE_HASH;
input_length &= 15;
if (unlikely(cbcmac && input_length)) {
token[0].stat = 0;
token[1].opcode = EIP197_TOKEN_OPCODE_INSERT;
token[1].packet_length = 16 - input_length;
token[1].stat = EIP197_TOKEN_STAT_LAST_HASH;
token[1].instructions = EIP197_TOKEN_INS_TYPE_HASH;
} else {
token[0].stat = EIP197_TOKEN_STAT_LAST_HASH;
eip197_noop_token(&token[1]);
}
token[2].opcode = EIP197_TOKEN_OPCODE_INSERT;
token[2].stat = EIP197_TOKEN_STAT_LAST_HASH |
EIP197_TOKEN_STAT_LAST_PACKET;
token[2].packet_length = result_length;
token[2].instructions = EIP197_TOKEN_INS_TYPE_OUTPUT |
EIP197_TOKEN_INS_INSERT_HASH_DIGEST;
eip197_noop_token(&token[3]);
}
static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
struct safexcel_ahash_req *req,
struct safexcel_command_desc *cdesc)
{
struct safexcel_crypto_priv *priv = ctx->base.priv;
Annotation
- Immediate include surface: `crypto/aes.h`, `crypto/hmac.h`, `crypto/md5.h`, `crypto/sha1.h`, `crypto/sha2.h`, `crypto/sha3.h`, `crypto/skcipher.h`, `crypto/sm3.h`.
- Detected declarations: `struct safexcel_ahash_ctx`, `struct safexcel_ahash_req`, `function safexcel_queued_len`, `function safexcel_hash_token`, `function safexcel_context_control`, `function safexcel_handle_req_result`, `function safexcel_ahash_send_req`, `function for_each_sg`, `function safexcel_handle_inv_result`, `function safexcel_handle_result`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.