drivers/crypto/intel/keembay/keembay-ocs-ecc.c
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/keembay/keembay-ocs-ecc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/keembay/keembay-ocs-ecc.c- Extension
.c- Size
- 26768 bytes
- Lines
- 999
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/ecc_curve.hcrypto/ecdh.hcrypto/engine.hcrypto/internal/ecc.hcrypto/internal/kpp.hcrypto/kpp.hcrypto/rng.hlinux/clk.hlinux/completion.hlinux/err.hlinux/fips.hlinux/interrupt.hlinux/io.hlinux/iopoll.hlinux/irq.hlinux/kernel.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/scatterlist.hlinux/string.h
Detected Declarations
struct ocs_ecc_devstruct ocs_ecc_ctxstruct ocs_ecc_drvfunction digits_to_bytesfunction ocs_ecc_wait_idlefunction ocs_ecc_cmd_startfunction ocs_ecc_write_cmd_and_datafunction ocs_ecc_trigger_opfunction ocs_ecc_read_cx_outfunction ocs_ecc_read_cy_outfunction kmb_ecc_point_multfunction kmb_ecc_do_scalar_opfunction kmb_ocs_ecc_is_pubkey_valid_partialfunction kmb_ocs_ecc_is_pubkey_valid_fullfunction kmb_ecc_is_key_validfunction kmb_ecc_gen_privkeyfunction kmb_ocs_ecdh_set_secretfunction kmb_ecc_do_shared_secretfunction kmb_ecc_do_public_keyfunction kmb_ocs_ecc_do_one_requestfunction kmb_ocs_ecdh_generate_public_keyfunction kmb_ocs_ecdh_compute_shared_secretfunction kmb_ecc_tctx_initfunction kmb_ocs_ecdh_nist_p256_init_tfmfunction kmb_ocs_ecdh_nist_p384_init_tfmfunction kmb_ocs_ecdh_exit_tfmfunction kmb_ocs_ecdh_max_sizefunction ocs_ecc_irq_handlerfunction kmb_ocs_ecc_probefunction kmb_ocs_ecc_remove
Annotated Snippet
struct ocs_ecc_dev {
struct list_head list;
struct device *dev;
void __iomem *base_reg;
struct crypto_engine *engine;
struct completion irq_done;
int irq;
};
/**
* struct ocs_ecc_ctx - Transformation context.
* @ecc_dev: The ECC driver associated with this context.
* @curve: The elliptic curve used by this transformation.
* @private_key: The private key.
*/
struct ocs_ecc_ctx {
struct ocs_ecc_dev *ecc_dev;
const struct ecc_curve *curve;
u64 private_key[KMB_ECC_VLI_MAX_DIGITS];
};
/* Driver data. */
struct ocs_ecc_drv {
struct list_head dev_list;
spinlock_t lock; /* Protects dev_list. */
};
/* Global variable holding the list of OCS ECC devices (only one expected). */
static struct ocs_ecc_drv ocs_ecc = {
.dev_list = LIST_HEAD_INIT(ocs_ecc.dev_list),
.lock = __SPIN_LOCK_UNLOCKED(ocs_ecc.lock),
};
/* Get OCS ECC tfm context from kpp_request. */
static inline struct ocs_ecc_ctx *kmb_ocs_ecc_tctx(struct kpp_request *req)
{
return kpp_tfm_ctx(crypto_kpp_reqtfm(req));
}
/* Converts number of digits to number of bytes. */
static inline unsigned int digits_to_bytes(unsigned int n)
{
return n << ECC_DIGITS_TO_BYTES_SHIFT;
}
/*
* Wait for ECC idle i.e when an operation (other than write operations)
* is done.
*/
static inline int ocs_ecc_wait_idle(struct ocs_ecc_dev *dev)
{
u32 value;
return readl_poll_timeout((dev->base_reg + HW_OFFS_OCS_ECC_STATUS),
value,
!(value & HW_OCS_ECC_ISR_INT_STATUS_DONE),
POLL_USEC, TIMEOUT_USEC);
}
static void ocs_ecc_cmd_start(struct ocs_ecc_dev *ecc_dev, u32 op_size)
{
iowrite32(op_size | HW_OCS_ECC_COMMAND_START_VAL,
ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
}
/* Direct write of u32 buffer to ECC engine with associated instruction. */
static void ocs_ecc_write_cmd_and_data(struct ocs_ecc_dev *dev,
u32 op_size,
u32 inst,
const void *data_in,
size_t data_size)
{
iowrite32(op_size | inst, dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
/* MMIO Write src uint32 to dst. */
memcpy_toio(dev->base_reg + HW_OFFS_OCS_ECC_DATA_IN, data_in,
data_size);
}
/* Start OCS ECC operation and wait for its completion. */
static int ocs_ecc_trigger_op(struct ocs_ecc_dev *ecc_dev, u32 op_size,
u32 inst)
{
reinit_completion(&ecc_dev->irq_done);
iowrite32(ECC_ENABLE_INTR, ecc_dev->base_reg + HW_OFFS_OCS_ECC_IER);
iowrite32(op_size | inst, ecc_dev->base_reg + HW_OFFS_OCS_ECC_COMMAND);
return wait_for_completion_interruptible(&ecc_dev->irq_done);
}
Annotation
- Immediate include surface: `crypto/ecc_curve.h`, `crypto/ecdh.h`, `crypto/engine.h`, `crypto/internal/ecc.h`, `crypto/internal/kpp.h`, `crypto/kpp.h`, `crypto/rng.h`, `linux/clk.h`.
- Detected declarations: `struct ocs_ecc_dev`, `struct ocs_ecc_ctx`, `struct ocs_ecc_drv`, `function digits_to_bytes`, `function ocs_ecc_wait_idle`, `function ocs_ecc_cmd_start`, `function ocs_ecc_write_cmd_and_data`, `function ocs_ecc_trigger_op`, `function ocs_ecc_read_cx_out`, `function ocs_ecc_read_cy_out`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.