drivers/crypto/intel/keembay/ocs-aes.c
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/keembay/ocs-aes.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/keembay/ocs-aes.c- Extension
.c- Size
- 43449 bytes
- Lines
- 1490
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/interrupt.hlinux/kernel.hlinux/platform_device.hlinux/slab.hlinux/swab.hasm/byteorder.hasm/errno.hcrypto/aes.hcrypto/gcm.hocs-aes.h
Detected Declarations
struct ocs_dma_linked_listenum aes_counter_modefunction aes_a_set_endiannessfunction aes_a_op_triggerfunction aes_a_op_terminationfunction aes_a_set_last_gcxfunction aes_a_wait_last_gcxfunction aes_a_dma_wait_input_buffer_occupancyfunction registerfunction aes_a_dma_set_xfer_size_zerofunction aes_a_dma_activefunction aes_a_dma_active_src_ll_enfunction aes_a_dma_active_dst_ll_enfunction aes_a_dma_active_src_dst_ll_enfunction aes_a_dma_reset_and_activate_perf_cntrfunction aes_a_dma_wait_and_deactivate_perf_cntrfunction aes_irq_disablefunction aes_irq_enablefunction ocs_aes_irq_enable_and_waitfunction dma_to_ocs_aes_llfunction dma_from_ocs_aes_llfunction ocs_aes_irq_handlerfunction ocs_aes_set_keyfunction set_ocs_aes_commandfunction ocs_aes_initfunction ocs_aes_write_last_data_blk_lenfunction ocs_aes_validate_inputsfunction ocs_aes_opfunction ocs_aes_gcm_write_j0function ocs_aes_gcm_read_tagfunction ocs_aes_gcm_opfunction ocs_aes_ccm_write_encrypted_tagfunction ocs_aes_ccm_write_b0function ocs_aes_ccm_write_adata_lenfunction adata_lenfunction ocs_aes_ccm_do_adatafunction ocs_aes_ccm_encrypt_do_payloadfunction ocs_aes_ccm_decrypt_do_payloadfunction ccm_compare_tag_to_yrfunction ocs_aes_ccm_opfunction ocs_create_linked_list_from_sg
Annotated Snippet
struct ocs_dma_linked_list {
u32 src_addr;
u32 src_len;
u32 next;
u32 ll_flags;
} __packed;
/*
* Set endianness of inputs and outputs
* AES_BYTE_ORDER_CFG
* default 0x00000000
* bit [10] - KEY_HI_LO_SWAP
* bit [9] - KEY_HI_SWAP_DWORDS_IN_OCTWORD
* bit [8] - KEY_HI_SWAP_BYTES_IN_DWORD
* bit [7] - KEY_LO_SWAP_DWORDS_IN_OCTWORD
* bit [6] - KEY_LO_SWAP_BYTES_IN_DWORD
* bit [5] - IV_SWAP_DWORDS_IN_OCTWORD
* bit [4] - IV_SWAP_BYTES_IN_DWORD
* bit [3] - DOUT_SWAP_DWORDS_IN_OCTWORD
* bit [2] - DOUT_SWAP_BYTES_IN_DWORD
* bit [1] - DOUT_SWAP_DWORDS_IN_OCTWORD
* bit [0] - DOUT_SWAP_BYTES_IN_DWORD
*/
static inline void aes_a_set_endianness(const struct ocs_aes_dev *aes_dev)
{
iowrite32(0x7FF, aes_dev->base_reg + AES_BYTE_ORDER_CFG_OFFSET);
}
/* Trigger AES process start. */
static inline void aes_a_op_trigger(const struct ocs_aes_dev *aes_dev)
{
iowrite32(AES_ACTIVE_TRIGGER, aes_dev->base_reg + AES_ACTIVE_OFFSET);
}
/* Indicate last bulk of data. */
static inline void aes_a_op_termination(const struct ocs_aes_dev *aes_dev)
{
iowrite32(AES_ACTIVE_TERMINATION,
aes_dev->base_reg + AES_ACTIVE_OFFSET);
}
/*
* Set LAST_CCM_GCM in AES_ACTIVE register and clear all other bits.
*
* Called when DMA is programmed to fetch the last batch of data.
* - For AES-CCM it is called for the last batch of Payload data and Ciphertext
* data.
* - For AES-GCM, it is called for the last batch of Plaintext data and
* Ciphertext data.
*/
static inline void aes_a_set_last_gcx(const struct ocs_aes_dev *aes_dev)
{
iowrite32(AES_ACTIVE_LAST_CCM_GCM,
aes_dev->base_reg + AES_ACTIVE_OFFSET);
}
/* Wait for LAST_CCM_GCM bit to be unset. */
static inline void aes_a_wait_last_gcx(const struct ocs_aes_dev *aes_dev)
{
u32 aes_active_reg;
do {
aes_active_reg = ioread32(aes_dev->base_reg +
AES_ACTIVE_OFFSET);
} while (aes_active_reg & AES_ACTIVE_LAST_CCM_GCM);
}
/* Wait for 10 bits of input occupancy. */
static void aes_a_dma_wait_input_buffer_occupancy(const struct ocs_aes_dev *aes_dev)
{
u32 reg;
do {
reg = ioread32(aes_dev->base_reg + AES_A_DMA_STATUS_OFFSET);
} while (reg & AES_DMA_STATUS_INPUT_BUFFER_OCCUPANCY_MASK);
}
/*
* Set LAST_CCM_GCM and LAST_ADATA bits in AES_ACTIVE register (and clear all
* other bits).
*
* Called when DMA is programmed to fetch the last batch of Associated Data
* (CCM case) or Additional Authenticated Data (GCM case).
*/
static inline void aes_a_set_last_gcx_and_adata(const struct ocs_aes_dev *aes_dev)
{
iowrite32(AES_ACTIVE_LAST_ADATA | AES_ACTIVE_LAST_CCM_GCM,
aes_dev->base_reg + AES_ACTIVE_OFFSET);
}
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/interrupt.h`, `linux/kernel.h`, `linux/platform_device.h`, `linux/slab.h`, `linux/swab.h`, `asm/byteorder.h`, `asm/errno.h`.
- Detected declarations: `struct ocs_dma_linked_list`, `enum aes_counter_mode`, `function aes_a_set_endianness`, `function aes_a_op_trigger`, `function aes_a_op_termination`, `function aes_a_set_last_gcx`, `function aes_a_wait_last_gcx`, `function aes_a_dma_wait_input_buffer_occupancy`, `function register`, `function aes_a_dma_set_xfer_size_zero`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.