drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
Extension
.c
Size
31814 bytes
Lines
1086
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct adf_ring_config {
	u32 ring_mask;
	enum adf_cfg_service_type ring_type;
	const unsigned long *thrd_mask;
};

static u32 rmask_two_services[] = {
	RP_GROUP_0_MASK,
	RP_GROUP_1_MASK,
};

enum adf_gen6_rps {
	RP0 = 0,
	RP1 = 1,
	RP2 = 2,
	RP3 = 3,
	RP_MAX = RP3
};

/*
 * thrd_mask_[sym|asym|cpr|dcc]: these static arrays define the thread
 * configuration for handling requests of specific services across the
 * accelerator engines. Each element in an array corresponds to an
 * accelerator engine, with the value being a bitmask that specifies which
 * threads within that engine are capable of processing the particular service.
 *
 * For example, a value of 0x0C means that threads 2 and 3 are enabled for the
 * service in the respective accelerator engine.
 */
static const unsigned long thrd_mask_sym[ADF_6XXX_MAX_ACCELENGINES] = {
	0x0C, 0x0C, 0x0C, 0x0C, 0x1C, 0x1C, 0x1C, 0x1C, 0x00
};

static const unsigned long thrd_mask_asym[ADF_6XXX_MAX_ACCELENGINES] = {
	0x70, 0x70, 0x70, 0x70, 0x60, 0x60, 0x60, 0x60, 0x00
};

static const unsigned long thrd_mask_cpr[ADF_6XXX_MAX_ACCELENGINES] = {
	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00
};

static const unsigned long thrd_mask_dcc[ADF_6XXX_MAX_ACCELENGINES] = {
	0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x03, 0x03, 0x00
};

static const unsigned long thrd_mask_dcpr[ADF_6XXX_MAX_ACCELENGINES] = {
	0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00
};

static const unsigned long thrd_mask_wcy[ADF_6XXX_MAX_ACCELENGINES] = {
	0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x00
};

static const char *const adf_6xxx_fw_objs[] = {
	[ADF_FW_CY_OBJ] = ADF_6XXX_CY_OBJ,
	[ADF_FW_DC_OBJ] = ADF_6XXX_DC_OBJ,
	[ADF_FW_ADMIN_OBJ] = ADF_6XXX_ADMIN_OBJ,
	[ADF_FW_WCY_OBJ] = ADF_6XXX_WCY_OBJ,
};

static const struct adf_fw_config adf_default_fw_config[] = {
	{ ADF_AE_GROUP_1, ADF_FW_DC_OBJ },
	{ ADF_AE_GROUP_0, ADF_FW_CY_OBJ },
	{ ADF_AE_GROUP_2, ADF_FW_ADMIN_OBJ },
};

static const struct adf_fw_config adf_wcy_fw_config[] = {
	{ ADF_AE_GROUP_1, ADF_FW_WCY_OBJ },
	{ ADF_AE_GROUP_0, ADF_FW_WCY_OBJ },
	{ ADF_AE_GROUP_2, ADF_FW_ADMIN_OBJ },
};

static struct adf_hw_device_class adf_6xxx_class = {
	.name = ADF_6XXX_DEVICE_NAME,
	.type = DEV_6XXX,
};

static bool services_supported(unsigned long mask)
{
	int num_svc;

	if (mask >= BIT(SVC_COUNT))
		return false;

	num_svc = hweight_long(mask);
	switch (num_svc) {
	case ADF_ONE_SERVICE:
		return true;
	case ADF_TWO_SERVICES:
	case ADF_THREE_SERVICES:

Annotation

Implementation Notes