drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h
Extension
.h
Size
6562 bytes
Lines
198
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ADF_6XXX_HW_DATA_H_
#define ADF_6XXX_HW_DATA_H_

#include <linux/bits.h>
#include <linux/time.h>
#include <linux/units.h>

#include "adf_accel_devices.h"
#include "adf_cfg_common.h"
#include "adf_dc.h"

/* PCIe configuration space */
#define ADF_GEN6_BAR_MASK		(BIT(0) | BIT(2) | BIT(4))
#define ADF_GEN6_SRAM_BAR		0
#define ADF_GEN6_PMISC_BAR		1
#define ADF_GEN6_ETR_BAR		2
#define ADF_6XXX_MAX_ACCELENGINES	9

/* Clocks frequency */
#define ADF_GEN6_COUNTER_FREQ		(100 * HZ_PER_MHZ)

/* Physical function fuses */
#define ADF_GEN6_FUSECTL0_OFFSET	0x2C8
#define ADF_GEN6_FUSECTL1_OFFSET	0x2CC
#define ADF_GEN6_FUSECTL4_OFFSET	0x2D8

/* Accelerators */
#define ADF_GEN6_ACCELERATORS_MASK	0x1
#define ADF_GEN6_MAX_ACCELERATORS	1

/* MSI-X interrupt */
#define ADF_GEN6_SMIAPF_RP_X0_MASK_OFFSET	0x41A040
#define ADF_GEN6_SMIAPF_RP_X1_MASK_OFFSET	0x41A044
#define ADF_GEN6_SMIAPF_MASK_OFFSET		0x41A084
#define ADF_GEN6_MSIX_RTTABLE_OFFSET(i)		(0x409000 + ((i) * 4))

/* Bank and ring configuration */
#define ADF_GEN6_NUM_RINGS_PER_BANK	2
#define ADF_GEN6_NUM_BANKS_PER_VF	4
#define ADF_GEN6_ETR_MAX_BANKS		64
#define ADF_GEN6_RX_RINGS_OFFSET	1
#define ADF_GEN6_TX_RINGS_MASK		0x1

/* Arbiter configuration */
#define ADF_GEN6_ARB_CONFIG			(BIT(31) | BIT(6) | BIT(0))
#define ADF_GEN6_ARB_OFFSET			0x000
#define ADF_GEN6_ARB_WRK_2_SER_MAP_OFFSET	0x400

/* Admin interface configuration */
#define ADF_GEN6_ADMINMSGUR_OFFSET	0x500574
#define ADF_GEN6_ADMINMSGLR_OFFSET	0x500578
#define ADF_GEN6_MAILBOX_BASE_OFFSET	0x600970

/* Anti-rollback */
#define ADF_GEN6_SVNCHECK_CSR_MSG	0x640004

/* Fuse bits */
#define ADF_GEN6_ANTI_RB_FUSE_BIT	BIT(24)
#define ADF_GEN6_KPT_FUSE_BIT		BIT(16)

/*
 * Watchdog timers
 * Timeout is in cycles. Clock speed may vary across products but this
 * value should be a few milli-seconds.
 */
#define ADF_SSM_WDT_DEFAULT_VALUE	0x7000000ULL
#define ADF_SSM_WDT_PKE_DEFAULT_VALUE	0x8000000ULL
#define ADF_SSMWDTATHL_OFFSET		0x5208
#define ADF_SSMWDTATHH_OFFSET		0x520C
#define ADF_SSMWDTCNVL_OFFSET		0x5408
#define ADF_SSMWDTCNVH_OFFSET		0x540C
#define ADF_SSMWDTWCPL_OFFSET		0x5608
#define ADF_SSMWDTWCPH_OFFSET		0x560C
#define ADF_SSMWDTUCSL_OFFSET		0x5808
#define ADF_SSMWDTUCSH_OFFSET		0x580C
#define ADF_SSMWDTDCPRL_OFFSET		0x5A08
#define ADF_SSMWDTDCPRH_OFFSET		0x5A0C
#define ADF_SSMWDTWATL_OFFSET		0x5C08
#define ADF_SSMWDTWATH_OFFSET		0x5C0C
#define ADF_SSMWDTPKEL_OFFSET		0x5E08
#define ADF_SSMWDTPKEH_OFFSET		0x5E0C

/* Ring reset */
#define ADF_RPRESET_POLL_TIMEOUT_US	(5 * USEC_PER_SEC)
#define ADF_RPRESET_POLL_DELAY_US	20
#define ADF_WQM_CSR_RPRESETCTL_RESET	BIT(0)
#define ADF_WQM_CSR_RPRESETCTL(bank)	(0x6000 + (bank) * 8)
#define ADF_WQM_CSR_RPRESETSTS_STATUS	BIT(0)
#define ADF_WQM_CSR_RPRESETSTS(bank)	(ADF_WQM_CSR_RPRESETCTL(bank) + 4)

Annotation

Implementation Notes