drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h- Extension
.h- Size
- 16529 bytes
- Lines
- 507
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/interrupt.hlinux/module.hlinux/list.hlinux/io.hlinux/pci.hlinux/ratelimit.hlinux/types.hlinux/qat/qat_mig_dev.hlinux/wordpart.hadf_anti_rb.hadf_cfg_common.hadf_dc.hadf_kpt.hadf_rl.hadf_telemetry.hadf_pfvf_msg.hicp_qat_hw.h
Detected Declarations
struct adf_barstruct adf_irqstruct adf_accel_msixstruct adf_accel_pcistruct adf_error_countersstruct adf_hw_device_classstruct arb_infostruct admin_infostruct adf_bank_statestruct adf_hw_csr_opsstruct adf_cfg_device_datastruct adf_accel_devstruct adf_etr_datastruct adf_etr_ring_datastruct adf_ras_opsstruct adf_pfvf_opsstruct adf_dc_opsstruct qat_migdev_opsstruct adf_dev_err_maskstruct adf_hw_device_datastruct adf_admin_commsstruct icp_qat_fw_loader_handlestruct adf_fw_loader_datastruct adf_accel_vf_infostruct adf_dc_datastruct adf_pmstruct adf_sysfsstruct adf_accel_devenum adf_accel_capabilitiesenum adf_accel_capabilities_extenum adf_fusesenum dev_stateenum dev_sku_infoenum ras_errors
Annotated Snippet
struct adf_bar {
resource_size_t base_addr;
void __iomem *virt_addr;
resource_size_t size;
};
struct adf_irq {
bool enabled;
char name[ADF_MAX_MSIX_VECTOR_NAME];
};
struct adf_accel_msix {
struct adf_irq *irqs;
u32 num_entries;
};
struct adf_accel_pci {
struct pci_dev *pci_dev;
struct adf_accel_msix msix_entries;
struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
u8 revid;
u8 sku;
};
enum dev_state {
DEV_DOWN = 0,
DEV_UP
};
enum dev_sku_info {
DEV_SKU_1 = 0,
DEV_SKU_2,
DEV_SKU_3,
DEV_SKU_4,
DEV_SKU_VF,
DEV_SKU_UNKNOWN,
};
enum ras_errors {
ADF_RAS_CORR,
ADF_RAS_UNCORR,
ADF_RAS_FATAL,
ADF_RAS_ERRORS,
};
struct adf_error_counters {
atomic_t counter[ADF_RAS_ERRORS];
bool sysfs_added;
bool enabled;
};
static inline const char *get_sku_info(enum dev_sku_info info)
{
switch (info) {
case DEV_SKU_1:
return "SKU1";
case DEV_SKU_2:
return "SKU2";
case DEV_SKU_3:
return "SKU3";
case DEV_SKU_4:
return "SKU4";
case DEV_SKU_VF:
return "SKUVF";
case DEV_SKU_UNKNOWN:
default:
break;
}
return "Unknown SKU";
}
struct adf_hw_device_class {
const char *name;
const enum adf_device_type type;
u32 instances;
};
struct arb_info {
u32 arb_cfg;
u32 arb_offset;
u32 wt2sam_offset;
};
struct admin_info {
u32 admin_msg_ur;
u32 admin_msg_lr;
u32 mailbox_offset;
};
struct adf_bank_state;
Annotation
- Immediate include surface: `linux/interrupt.h`, `linux/module.h`, `linux/list.h`, `linux/io.h`, `linux/pci.h`, `linux/ratelimit.h`, `linux/types.h`, `linux/qat/qat_mig_dev.h`.
- Detected declarations: `struct adf_bar`, `struct adf_irq`, `struct adf_accel_msix`, `struct adf_accel_pci`, `struct adf_error_counters`, `struct adf_hw_device_class`, `struct arb_info`, `struct admin_info`, `struct adf_bank_state`, `struct adf_hw_csr_ops`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.