drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
Extension
.c
Size
6815 bytes
Lines
232
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2024 Intel Corporation */
#include <linux/types.h>
#include "adf_gen4_hw_csr_data.h"

static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
{
	return BUILD_RING_BASE_ADDR(addr, size);
}

static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
{
	return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
}

static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
				u32 value)
{
	WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
}

static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
{
	return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
}

static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
				u32 value)
{
	WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
}

static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_STAT(csr_base_addr, bank);
}

static u32 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_UO_STAT(csr_base_addr, bank);
}

static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_E_STAT(csr_base_addr, bank);
}

static u32 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_NE_STAT(csr_base_addr, bank);
}

static u32 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_NF_STAT(csr_base_addr, bank);
}

static u32 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_F_STAT(csr_base_addr, bank);
}

static u32 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_C_STAT(csr_base_addr, bank);
}

static u32 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_EXP_STAT(csr_base_addr, bank);
}

static u32 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank)
{
	return READ_CSR_EXP_INT_EN(csr_base_addr, bank);
}

static void write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank,
				 u32 value)
{
	WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value);
}

static u32 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
				u32 ring)
{
	return READ_CSR_RING_CONFIG(csr_base_addr, bank, ring);
}

static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,

Annotation

Implementation Notes