drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.c
Extension
.c
Size
25519 bytes
Lines
819
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (atufaultstatus) {
			dev_err(&GET_DEV(accel_dev), "Ring pair (%u) ATU detected fault: %#x\n", i,
				atufaultstatus);
			ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
			ADF_CSR_WR(csr, ADF_GEN6_ATUFAULTSTATUS(i), atufaultstatus);
		}
	}
}

static void adf_handle_rlterror(struct adf_accel_dev *accel_dev, void __iomem *csr,
				u32 errsou)
{
	u32 rlterror;

	if (!(errsou & ADF_GEN6_ERRSOU3_RLTERROR_BIT))
		return;

	rlterror = ADF_CSR_RD(csr, ADF_GEN6_RLT_ERRLOG);
	rlterror &= ADF_GEN6_RLT_ERRLOG_MASK;
	if (rlterror) {
		dev_err(&GET_DEV(accel_dev), "Error in rate limiting block: %#x\n", rlterror);
		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
		ADF_CSR_WR(csr, ADF_GEN6_RLT_ERRLOG, rlterror);
	}
}

static void adf_handle_vflr(struct adf_accel_dev *accel_dev, void __iomem *csr, u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_VFLRNOTIFY_BIT))
		return;

	dev_err(&GET_DEV(accel_dev), "Uncorrectable error in VF\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);
}

static void adf_handle_tc_vc_map_error(struct adf_accel_dev *accel_dev, void __iomem *csr,
				       u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_TC_VC_MAP_ERROR_BIT))
		return;

	dev_err(&GET_DEV(accel_dev), "Violation of PCIe TC VC mapping\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
}

static void adf_handle_pcie_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
				    u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_PCIE_DEVHALT_BIT))
		return;

	dev_err(&GET_DEV(accel_dev),
		"DEVHALT due to an error in an incoming transaction\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
}

static void adf_handle_pg_req_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
				      u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_PG_REQ_DEVHALT_BIT))
		return;

	dev_err(&GET_DEV(accel_dev),
		"Error due to response failure in response to a page request\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
}

static void adf_handle_xlt_cpl_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
				       u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_XLT_CPL_DEVHALT_BIT))
		return;

	dev_err(&GET_DEV(accel_dev), "Error status for a address translation request\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
}

static void adf_handle_ti_int_err_devhalt(struct adf_accel_dev *accel_dev, void __iomem *csr,
					  u32 errsou)
{
	if (!(errsou & ADF_GEN6_ERRSOU3_TI_INT_ERR_DEVHALT_BIT))
		return;

	dev_err(&GET_DEV(accel_dev), "DEVHALT due to a TI internal memory error\n");
	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_FATAL);
}

static void adf_gen6_process_errsou3(struct adf_accel_dev *accel_dev, void __iomem *csr,
				     u32 errsou)
{

Annotation

Implementation Notes