drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/adf_gen6_ras.h- Extension
.h- Size
- 17572 bytes
- Lines
- 505
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.h
Detected Declarations
struct adf_ras_ops
Annotated Snippet
#ifndef ADF_GEN6_RAS_H_
#define ADF_GEN6_RAS_H_
#include <linux/bits.h>
struct adf_ras_ops;
/* Error source registers */
#define ADF_GEN6_ERRSOU0 0x41A200
#define ADF_GEN6_ERRSOU1 0x41A204
#define ADF_GEN6_ERRSOU2 0x41A208
#define ADF_GEN6_ERRSOU3 0x41A20C
/* Error source mask registers */
#define ADF_GEN6_ERRMSK0 0x41A210
#define ADF_GEN6_ERRMSK1 0x41A214
#define ADF_GEN6_ERRMSK2 0x41A218
#define ADF_GEN6_ERRMSK3 0x41A21C
/* ERRSOU0 Correctable error mask */
#define ADF_GEN6_ERRSOU0_MASK BIT(0)
#define ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT BIT(0)
#define ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT BIT(1)
#define ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT BIT(2)
#define ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT BIT(3)
#define ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT BIT(4)
#define ADF_GEN6_ERRSOU1_MASK ( \
(ADF_GEN6_ERRSOU1_CPP0_MEUNC_BIT) | \
(ADF_GEN6_ERRSOU1_CPP_CMDPARERR_BIT) | \
(ADF_GEN6_ERRSOU1_RIMEM_PARERR_STS_BIT) | \
(ADF_GEN6_ERRSOU1_TIMEM_PARERR_STS_BIT) | \
(ADF_GEN6_ERRSOU1_SFICMD_PARERR_BIT))
#define ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT BIT(0)
#define ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT BIT(1)
#define ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT BIT(2)
#define ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT BIT(3)
#define ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT BIT(4)
#define ADF_GEN6_ERRMSK1_MASK ( \
(ADF_GEN6_ERRMSK1_CPP0_MEUNC_BIT) | \
(ADF_GEN6_ERRMSK1_CPP_CMDPARERR_BIT) | \
(ADF_GEN6_ERRMSK1_RIMEM_PARERR_STS_BIT) | \
(ADF_GEN6_ERRMSK1_TIMEM_PARERR_STS_BIT) | \
(ADF_GEN6_ERRMSK1_IOSFCMD_PARERR_BIT))
/* HI AE Uncorrectable error log */
#define ADF_GEN6_HIAEUNCERRLOG_CPP0 0x41A300
/* HI AE Uncorrectable error log enable */
#define ADF_GEN6_HIAEUNCERRLOGENABLE_CPP0 0x41A320
/* HI AE Correctable error log */
#define ADF_GEN6_HIAECORERRLOG_CPP0 0x41A308
/* HI AE Correctable error log enable */
#define ADF_GEN6_HIAECORERRLOGENABLE_CPP0 0x41A318
/* HI CPP Agent Command parity error log */
#define ADF_GEN6_HICPPAGENTCMDPARERRLOG 0x41A310
/* HI CPP Agent command parity error logging enable */
#define ADF_GEN6_HICPPAGENTCMDPARERRLOGENABLE 0x41A314
#define ADF_6XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1B
/* RI Memory parity error status register */
#define ADF_GEN6_RIMEM_PARERR_STS 0x41B128
/* RI Memory parity error reporting enable */
#define ADF_GEN6_RI_MEM_PAR_ERR_EN0 0x41B12C
/*
* RI Memory parity error mask
* BIT(4) - ri_tlq_phdr parity error
* BIT(5) - ri_tlq_pdata parity error
* BIT(6) - ri_tlq_nphdr parity error
* BIT(7) - ri_tlq_npdata parity error
* BIT(8) - ri_tlq_cplhdr parity error
* BIT(10) - BIT(13) - ri_tlq_cpldata[0:3] parity error
* BIT(19) - ri_cds_cmd_fifo parity error
* BIT(20) - ri_obc_ricpl_fifo parity error
* BIT(21) - ri_obc_tiricpl_fifo parity error
* BIT(22) - ri_obc_cppcpl_fifo parity error
* BIT(23) - ri_obc_pendcpl_fifo parity error
* BIT(24) - ri_cpp_cmd_fifo parity error
* BIT(25) - ri_cds_ticmd_fifo parity error
* BIT(26) - riti_cmd_fifo parity error
Annotation
- Immediate include surface: `linux/bits.h`.
- Detected declarations: `struct adf_ras_ops`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.