drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c
Extension
.c
Size
10526 bytes
Lines
259
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2025 Intel Corporation. */
#include <linux/export.h>

#include "adf_gen6_tl.h"
#include "adf_telemetry.h"
#include "adf_tl_debugfs.h"
#include "icp_qat_fw_init_admin.h"

#define ADF_GEN6_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen6)

#define ADF_GEN6_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen6)

#define ADF_GEN6_TL_SL_UTIL_COUNTER(_name)			\
	ADF_TL_COUNTER("util_" #_name, ADF_TL_SIMPLE_COUNT,	\
			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen6))

#define ADF_GEN6_TL_SL_EXEC_COUNTER(_name)			\
	ADF_TL_COUNTER("exec_" #_name, ADF_TL_SIMPLE_COUNT,	\
			ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen6))

#define SLICE_IDX(sl) offsetof(struct icp_qat_fw_init_admin_slice_cnt, sl##_cnt)

#define ADF_GEN6_TL_CMDQ_WAIT_COUNTER(_name)                     \
	ADF_TL_COUNTER("cmdq_wait_" #_name, ADF_TL_SIMPLE_COUNT, \
		       ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_wait_cnt, gen6))
#define ADF_GEN6_TL_CMDQ_EXEC_COUNTER(_name)                     \
	ADF_TL_COUNTER("cmdq_exec_" #_name, ADF_TL_SIMPLE_COUNT, \
		       ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_exec_cnt, gen6))
#define ADF_GEN6_TL_CMDQ_DRAIN_COUNTER(_name)                            \
	ADF_TL_COUNTER("cmdq_drain_" #_name, ADF_TL_SIMPLE_COUNT,        \
		       ADF_TL_CMDQ_REG_OFF(_name, reg_tm_cmdq_drain_cnt, \
					   gen6))

#define CPR_QUEUE_COUNT		5
#define DCPR_QUEUE_COUNT	3
#define PKE_QUEUE_COUNT		1
#define WAT_QUEUE_COUNT		7
#define WCP_QUEUE_COUNT		7
#define USC_QUEUE_COUNT		3
#define ATH_QUEUE_COUNT		2

/* Device level counters. */
static const struct adf_tl_dbg_counter dev_counters[] = {
	/* PCIe partial transactions. */
	ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_prt_trans_cnt)),
	/* Max read latency[ns]. */
	ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
	/* Read latency average[ns]. */
	ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
	/* Max "get to put" latency[ns]. */
	ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
	/* "Get to put" latency average[ns]. */
	ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
	/* PCIe write bandwidth[Mbps]. */
	ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_in)),
	/* PCIe read bandwidth[Mbps]. */
	ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_out)),
	/* Page request latency average[ns]. */
	ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
	/* Page translation latency average[ns]. */
	ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
	/* Maximum uTLB used. */
	ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
		       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_max_utlb_used)),
	/* Ring Empty average[ns] across all rings */
	ADF_TL_COUNTER_LATENCY(RE_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_re_acc),
			       ADF_GEN6_TL_DEV_REG_OFF(reg_tl_re_cnt)),
};

/* Accelerator utilization counters */
static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
	/* Compression accelerator utilization. */
	[SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(cnv),
	/* Decompression accelerator utilization. */
	[SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(dcprz),

Annotation

Implementation Notes