drivers/crypto/intel/qat/qat_common/adf_rl_admin.h

File Facts

System

Linux kernel

Corpus path

drivers/crypto/intel/qat/qat_common/adf_rl_admin.h

Extension

.h

Size

536 bytes

Lines

19

Domain

Driver Families

Bucket

drivers/crypto

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/types.h
• adf_rl.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef ADF_RL_ADMIN_H_
#define ADF_RL_ADMIN_H_

#include <linux/types.h>

#include "adf_rl.h"

int adf_rl_send_admin_init_msg(struct adf_accel_dev *accel_dev,
			       struct rl_slice_cnt *slices_int);
int adf_rl_send_admin_add_update_msg(struct adf_accel_dev *accel_dev,
				     struct rl_sla *sla, bool is_update);
int adf_rl_send_admin_delete_msg(struct adf_accel_dev *accel_dev, u16 node_id,
				 u8 node_type);

#endif /* ADF_RL_ADMIN_H_ */

Annotation

• Immediate include surface: `linux/types.h`, `adf_rl.h`.
• Atlas domain: Driver Families / drivers/crypto.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.