drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/icp_qat_fw_comp.h
Extension
.h
Size
13676 bytes
Lines
424
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct icp_qat_fw_comp_req_hdr_cd_pars {
	union {
		struct {
			__u64 content_desc_addr;
			__u16 content_desc_resrvd1;
			__u8 content_desc_params_sz;
			__u8 content_desc_hdr_resrvd2;
			__u32 content_desc_resrvd3;
		} s;
		struct {
			__u32 comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
			__u32 content_desc_resrvd4;
		} sl;
	} u;
};

struct icp_qat_fw_comp_req_params {
	__u32 comp_len;
	__u32 out_buffer_sz;
	union {
		struct {
			__u32 initial_crc32;
			__u32 initial_adler;
		} legacy;
		__u64 crc_data_addr;
	} crc;
	__u32 req_par_flags;
	__u32 rsrvd;
};

#define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr, \
					      cnvdfx, crc, xxhash_acc, \
					      cnv_error_type, append_crc, \
					      drop_data, partial_decomp) \
	((((sop) & ICP_QAT_FW_COMP_SOP_MASK) << \
	ICP_QAT_FW_COMP_SOP_BITPOS) | \
	(((eop) & ICP_QAT_FW_COMP_EOP_MASK) << \
	ICP_QAT_FW_COMP_EOP_BITPOS) | \
	(((bfinal) & ICP_QAT_FW_COMP_BFINAL_MASK) \
	<< ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
	(((cnv) & ICP_QAT_FW_COMP_CNV_MASK) << \
	ICP_QAT_FW_COMP_CNV_BITPOS) | \
	(((cnvnr) & ICP_QAT_FW_COMP_CNVNR_MASK) \
	<< ICP_QAT_FW_COMP_CNVNR_BITPOS) | \
	(((cnvdfx) & ICP_QAT_FW_COMP_CNV_DFX_MASK) \
	<< ICP_QAT_FW_COMP_CNV_DFX_BITPOS) | \
	(((crc) & ICP_QAT_FW_COMP_CRC_MODE_MASK) \
	<< ICP_QAT_FW_COMP_CRC_MODE_BITPOS) | \
	(((xxhash_acc) & ICP_QAT_FW_COMP_XXHASH_ACC_MODE_MASK) \
	<< ICP_QAT_FW_COMP_XXHASH_ACC_MODE_BITPOS) | \
	(((cnv_error_type) & ICP_QAT_FW_COMP_CNV_ERROR_MASK) \
	<< ICP_QAT_FW_COMP_CNV_ERROR_BITPOS) | \
	(((append_crc) & ICP_QAT_FW_COMP_APPEND_CRC_MASK) \
	<< ICP_QAT_FW_COMP_APPEND_CRC_BITPOS) | \
	(((drop_data) & ICP_QAT_FW_COMP_DROP_DATA_MASK) \
	<< ICP_QAT_FW_COMP_DROP_DATA_BITPOS) | \
	(((partial_decomp) & ICP_QAT_FW_COMP_PARTIAL_DECOMP_MASK) \
	<< ICP_QAT_FW_COMP_PARTIAL_DECOMP_BITPOS))

#define ICP_QAT_FW_COMP_NOT_SOP 0
#define ICP_QAT_FW_COMP_SOP 1
#define ICP_QAT_FW_COMP_NOT_EOP 0
#define ICP_QAT_FW_COMP_EOP 1
#define ICP_QAT_FW_COMP_NOT_BFINAL 0
#define ICP_QAT_FW_COMP_BFINAL 1
#define ICP_QAT_FW_COMP_NO_CNV 0
#define ICP_QAT_FW_COMP_CNV 1
#define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
#define ICP_QAT_FW_COMP_CNV_RECOVERY 1
#define ICP_QAT_FW_COMP_NO_CNV_DFX 0
#define ICP_QAT_FW_COMP_CNV_DFX 1
#define ICP_QAT_FW_COMP_CRC_MODE_LEGACY 0
#define ICP_QAT_FW_COMP_CRC_MODE_E2E 1
#define ICP_QAT_FW_COMP_NO_XXHASH_ACC 0
#define ICP_QAT_FW_COMP_XXHASH_ACC 1
#define ICP_QAT_FW_COMP_APPEND_CRC 1
#define ICP_QAT_FW_COMP_NO_APPEND_CRC 0
#define ICP_QAT_FW_COMP_DROP_DATA 1
#define ICP_QAT_FW_COMP_NO_DROP_DATA 0
#define ICP_QAT_FW_COMP_PARTIAL_DECOMPRESS 1
#define ICP_QAT_FW_COMP_NO_PARTIAL_DECOMPRESS 0
#define ICP_QAT_FW_COMP_SOP_BITPOS 0
#define ICP_QAT_FW_COMP_SOP_MASK 0x1
#define ICP_QAT_FW_COMP_EOP_BITPOS 1
#define ICP_QAT_FW_COMP_EOP_MASK 0x1
#define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
#define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
#define ICP_QAT_FW_COMP_CNV_BITPOS 16
#define ICP_QAT_FW_COMP_CNV_MASK 0x1
#define ICP_QAT_FW_COMP_CNVNR_BITPOS 17

Annotation

Implementation Notes