drivers/crypto/intel/qat/qat_common/icp_qat_fw.h
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_fw.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/icp_qat_fw.h- Extension
.h- Size
- 9839 bytes
- Lines
- 306
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hicp_qat_hw.h
Detected Declarations
struct icp_qat_fw_comn_req_hdr_cd_parsstruct icp_qat_fw_comn_req_midstruct icp_qat_fw_comn_req_cd_ctrlstruct icp_qat_fw_comn_req_hdrstruct icp_qat_fw_comn_req_rqparsstruct icp_qat_fw_comn_reqstruct icp_qat_fw_comn_errorstruct icp_qat_fw_comn_resp_hdrstruct icp_qat_fw_comn_respenum icp_qat_fw_comn_resp_serv_idenum icp_qat_fw_comn_request_idenum icp_qat_fw_slice
Annotated Snippet
struct icp_qat_fw_comn_req_hdr_cd_pars {
union {
struct {
__u64 content_desc_addr;
__u16 content_desc_resrvd1;
__u8 content_desc_params_sz;
__u8 content_desc_hdr_resrvd2;
__u32 content_desc_resrvd3;
} s;
struct {
__u32 serv_specif_fields[4];
} s1;
} u;
};
struct icp_qat_fw_comn_req_mid {
__u64 opaque_data;
__u64 src_data_addr;
__u64 dest_data_addr;
__u32 src_length;
__u32 dst_length;
};
struct icp_qat_fw_comn_req_cd_ctrl {
__u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
};
struct icp_qat_fw_comn_req_hdr {
__u8 resrvd1;
__u8 service_cmd_id;
__u8 service_type;
__u8 hdr_flags;
__u16 serv_specif_flags;
__u16 comn_req_flags;
};
struct icp_qat_fw_comn_req_rqpars {
__u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
};
struct icp_qat_fw_comn_req {
struct icp_qat_fw_comn_req_hdr comn_hdr;
struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
struct icp_qat_fw_comn_req_mid comn_mid;
struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
};
struct icp_qat_fw_comn_error {
__u8 xlat_err_code;
__u8 cmp_err_code;
};
struct icp_qat_fw_comn_resp_hdr {
__u8 resrvd1;
__u8 service_id;
__u8 response_type;
__u8 hdr_flags;
struct icp_qat_fw_comn_error comn_error;
__u8 comn_status;
__u8 cmd_id;
};
struct icp_qat_fw_comn_resp {
struct icp_qat_fw_comn_resp_hdr comn_hdr;
__u64 opaque_data;
__u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
};
#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
#define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
#define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
#define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_type
#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
icp_qat_fw_comn_req_hdr_t.service_type = val
#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
icp_qat_fw_comn_req_hdr_t.service_cmd_id
#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
Annotation
- Immediate include surface: `linux/types.h`, `icp_qat_hw.h`.
- Detected declarations: `struct icp_qat_fw_comn_req_hdr_cd_pars`, `struct icp_qat_fw_comn_req_mid`, `struct icp_qat_fw_comn_req_cd_ctrl`, `struct icp_qat_fw_comn_req_hdr`, `struct icp_qat_fw_comn_req_rqpars`, `struct icp_qat_fw_comn_req`, `struct icp_qat_fw_comn_error`, `struct icp_qat_fw_comn_resp_hdr`, `struct icp_qat_fw_comn_resp`, `enum icp_qat_fw_comn_resp_serv_id`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.