drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h- Extension
.h- Size
- 4471 bytes
- Lines
- 224
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
icp_qat_fw.h
Detected Declarations
struct icp_qat_fw_init_admin_tl_rp_indexesstruct icp_qat_fw_init_admin_slice_cntstruct icp_qat_fw_init_admin_sla_config_paramsstruct icp_qat_fw_init_admin_reqstruct icp_qat_fw_init_admin_respstruct icp_qat_fw_init_admin_pm_infostruct icp_qat_fw_init_admin_kpt_cfgenum icp_qat_fw_init_admin_cmd_idenum icp_qat_fw_init_admin_resp_status
Annotated Snippet
struct icp_qat_fw_init_admin_tl_rp_indexes {
__u8 rp_num_index_0;
__u8 rp_num_index_1;
__u8 rp_num_index_2;
__u8 rp_num_index_3;
};
struct icp_qat_fw_init_admin_slice_cnt {
__u8 cpr_cnt;
__u8 xlt_cnt;
__u8 dcpr_cnt;
__u8 pke_cnt;
__u8 wat_cnt;
__u8 wcp_cnt;
__u8 ucs_cnt;
__u8 cph_cnt;
__u8 ath_cnt;
};
struct icp_qat_fw_init_admin_sla_config_params {
__u32 pcie_in_cir;
__u32 pcie_in_pir;
__u32 pcie_out_cir;
__u32 pcie_out_pir;
__u32 slice_util_cir;
__u32 slice_util_pir;
__u32 ae_util_cir;
__u32 ae_util_pir;
__u16 rp_ids[RL_MAX_RP_IDS];
};
struct icp_qat_fw_init_admin_req {
__u16 init_cfg_sz;
__u8 resrvd1;
__u8 cmd_id;
__u32 resrvd2;
__u64 opaque_data;
__u64 init_cfg_ptr;
union {
struct {
__u16 ibuf_size_in_kb;
__u16 resrvd3;
};
struct {
__u32 int_timer_ticks;
};
struct {
__u32 heartbeat_ticks;
};
struct {
__u16 node_id;
__u8 node_type;
__u8 svc_type;
__u8 resrvd5[3];
__u8 rp_count;
};
__u32 idle_filter;
struct icp_qat_fw_init_admin_tl_rp_indexes rp_indexes;
};
__u32 resrvd4;
} __packed;
struct icp_qat_fw_init_admin_resp {
__u8 flags;
__u8 resrvd1;
__u8 status;
__u8 cmd_id;
union {
__u32 resrvd2;
struct {
__u16 version_minor_num;
__u16 version_major_num;
};
__u32 extended_features;
struct {
__u16 error_count;
__u16 latest_error;
};
};
__u64 opaque_data;
union {
__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4];
struct {
__u32 version_patch_num;
__u8 context_id;
__u8 ae_id;
__u16 resrvd4;
__u64 resrvd5;
Annotation
- Immediate include surface: `icp_qat_fw.h`.
- Detected declarations: `struct icp_qat_fw_init_admin_tl_rp_indexes`, `struct icp_qat_fw_init_admin_slice_cnt`, `struct icp_qat_fw_init_admin_sla_config_params`, `struct icp_qat_fw_init_admin_req`, `struct icp_qat_fw_init_admin_resp`, `struct icp_qat_fw_init_admin_pm_info`, `struct icp_qat_fw_init_admin_kpt_cfg`, `enum icp_qat_fw_init_admin_cmd_id`, `enum icp_qat_fw_init_admin_resp_status`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.