drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp_defs.h

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp_defs.h

File Facts

System: Linux kernel
Corpus path: drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp_defs.h
Extension: .h
Size: 10972 bytes
Lines: 301
Domain: Driver Families
Bucket: drivers/crypto
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

enum icp_qat_hw_comp_20_scb_control
enum icp_qat_hw_comp_20_rmb_control
enum icp_qat_hw_comp_20_som_control
enum icp_qat_hw_comp_20_skip_hash_rd_control
enum icp_qat_hw_comp_20_scb_unload_control
enum icp_qat_hw_comp_20_disable_token_fusion_control
enum icp_qat_hw_comp_20_lbms
enum icp_qat_hw_comp_20_scb_mode_reset_mask
enum icp_qat_hw_comp_20_hbs_control
enum icp_qat_hw_comp_20_abd
enum icp_qat_hw_comp_20_lllbd_ctrl
enum icp_qat_hw_comp_20_search_depth
enum icp_qat_hw_comp_20_hw_comp_format
enum icp_qat_hw_comp_20_min_match_control
enum icp_qat_hw_comp_20_skip_hash_collision
enum icp_qat_hw_comp_20_skip_hash_update
enum icp_qat_hw_comp_20_byte_skip
enum icp_qat_hw_comp_20_extended_delay_match_mode
enum icp_qat_hw_decomp_20_speculative_decoder_control
enum icp_qat_hw_decomp_20_mini_cam_control
enum icp_qat_hw_decomp_20_hbs_control
enum icp_qat_hw_decomp_20_lbms
enum icp_qat_hw_decomp_20_hw_comp_format
enum icp_qat_hw_decomp_20_min_match_control
enum icp_qat_hw_decomp_20_lz4_block_checksum_present

Annotated Snippet

#ifndef _ICP_QAT_HW_20_COMP_DEFS_H
#define _ICP_QAT_HW_20_COMP_DEFS_H

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS 31
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1

enum icp_qat_hw_comp_20_scb_control {
	ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0,
	ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS 30
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1

enum icp_qat_hw_comp_20_rmb_control {
	ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0,
	ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS 28
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3

enum icp_qat_hw_comp_20_som_control {
	ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0,
	ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1,
	ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2,
	ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1

enum icp_qat_hw_comp_20_skip_hash_rd_control {
	ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
	ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS 26
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK 0x1

enum icp_qat_hw_comp_20_scb_unload_control {
	ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0,
	ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1

enum icp_qat_hw_comp_20_disable_token_fusion_control {
	ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0,
	ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS 19
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK 0x3

enum icp_qat_hw_comp_20_lbms {
	ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB = 0x0,
	ICP_QAT_HW_COMP_20_LBMS_LBMS_256KB = 0x1,
	ICP_QAT_HW_COMP_20_LBMS_LBMS_1MB = 0x2,
	ICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3,
};

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL \
	ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB

#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18
#define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK 0x1

enum icp_qat_hw_comp_20_scb_mode_reset_mask {
	ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0,
	ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1,

Annotation

Detected declarations: `enum icp_qat_hw_comp_20_scb_control`, `enum icp_qat_hw_comp_20_rmb_control`, `enum icp_qat_hw_comp_20_som_control`, `enum icp_qat_hw_comp_20_skip_hash_rd_control`, `enum icp_qat_hw_comp_20_scb_unload_control`, `enum icp_qat_hw_comp_20_disable_token_fusion_control`, `enum icp_qat_hw_comp_20_lbms`, `enum icp_qat_hw_comp_20_scb_mode_reset_mask`, `enum icp_qat_hw_comp_20_hbs_control`, `enum icp_qat_hw_comp_20_abd`.
Atlas domain: Driver Families / drivers/crypto.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.