drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/icp_qat_hw_20_comp.h
Extension
.h
Size
6611 bytes
Lines
167
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct icp_qat_hw_comp_20_config_csr_lower {
	enum icp_qat_hw_comp_20_extended_delay_match_mode edmm;
	enum icp_qat_hw_comp_20_hw_comp_format algo;
	enum icp_qat_hw_comp_20_search_depth sd;
	enum icp_qat_hw_comp_20_hbs_control hbs;
	enum icp_qat_hw_comp_20_abd abd;
	enum icp_qat_hw_comp_20_lllbd_ctrl lllbd;
	enum icp_qat_hw_comp_20_min_match_control mmctrl;
	enum icp_qat_hw_comp_20_skip_hash_collision hash_col;
	enum icp_qat_hw_comp_20_skip_hash_update hash_update;
	enum icp_qat_hw_comp_20_byte_skip skip_ctrl;
};

static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)
{
	u32 val32 = 0;

	QAT_FIELD_SET(val32, csr.algo,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
	QAT_FIELD_SET(val32, csr.sd,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
	QAT_FIELD_SET(val32, csr.edmm,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
	QAT_FIELD_SET(val32, csr.hbs,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.lllbd,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
	QAT_FIELD_SET(val32, csr.mmctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.hash_col,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
	QAT_FIELD_SET(val32, csr.hash_update,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
	QAT_FIELD_SET(val32, csr.skip_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
	QAT_FIELD_SET(val32, csr.abd, ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);

	return swab32(val32);
}

struct icp_qat_hw_comp_20_config_csr_upper {
	enum icp_qat_hw_comp_20_scb_control scb_ctrl;
	enum icp_qat_hw_comp_20_rmb_control rmb_ctrl;
	enum icp_qat_hw_comp_20_som_control som_ctrl;
	enum icp_qat_hw_comp_20_skip_hash_rd_control skip_hash_ctrl;
	enum icp_qat_hw_comp_20_scb_unload_control scb_unload_ctrl;
	enum icp_qat_hw_comp_20_disable_token_fusion_control disable_token_fusion_ctrl;
	enum icp_qat_hw_comp_20_lbms lbms;
	enum icp_qat_hw_comp_20_scb_mode_reset_mask scb_mode_reset;
	__u16 lazy;
	__u16 nice;
};

static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)
{
	u32 val32 = 0;

	QAT_FIELD_SET(val32, csr.scb_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.rmb_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.som_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.skip_hash_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.scb_unload_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
	QAT_FIELD_SET(val32, csr.lbms,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
		      ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);

Annotation

Implementation Notes