drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h

File Facts

System: Linux kernel
Corpus path: drivers/crypto/intel/qat/qat_common/icp_qat_hw_51_comp_defs.h
Extension: .h
Size: 14321 bytes
Lines: 319
Domain: Driver Families
Bucket: drivers/crypto
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

linux/bits.h

Detected Declarations

enum icp_qat_hw_comp_51_som_control
enum icp_qat_hw_comp_51_skip_hash_rd_control
enum icp_qat_hw_comp_51_bypass_compression
enum icp_qat_hw_comp_51_dmm_algorithm
enum icp_qat_hw_comp_51_token_fusion_internal_only
enum icp_qat_hw_comp_51_bms
enum icp_qat_hw_comp_51_scb_mode_reset_mask
enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en
enum icp_qat_hw_comp_51_cnv_disable
enum icp_qat_hw_comp_51_asb_disable
enum icp_qat_hw_comp_51_spec_decoder_internal_only
enum icp_qat_hw_comp_51_mini_xcam_internal_only
enum icp_qat_hw_comp_51_rep_off_enc_internal_only
enum icp_qat_hw_comp_51_prog_block_drop_internal_only
enum icp_qat_hw_comp_51_skip_hash_override_internal_only
enum icp_qat_hw_comp_51_hbs
enum icp_qat_hw_comp_51_abd
enum icp_qat_hw_comp_51_lllbd_ctrl
enum icp_qat_hw_comp_51_search_depth
enum icp_qat_hw_comp_51_format
enum icp_qat_hw_comp_51_min_match_control
enum icp_qat_hw_comp_51_skip_hash_collision
enum icp_qat_hw_comp_51_skip_hash_update
enum icp_qat_hw_comp_51_byte_skip
enum icp_qat_hw_comp_51_lz4_block_checksum
enum icp_qat_hw_decomp_51_discard_data
enum icp_qat_hw_decomp_51_bms
enum icp_qat_hw_decomp_51_zstd_frame_gen_dec_en
enum icp_qat_hw_decomp_51_spec_decoder_internal_only
enum icp_qat_hw_decomp_51_mini_xcam_internal_only
enum icp_qat_hw_decomp_51_hbs
enum icp_qat_hw_decomp_51_format
enum icp_qat_hw_decomp_51_lz4_block_checksum

Annotated Snippet

#ifndef ICP_QAT_HW_51_COMP_DEFS_H_
#define ICP_QAT_HW_51_COMP_DEFS_H_

#include <linux/bits.h>

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_BITPOS	28
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK		GENMASK(1, 0)
enum icp_qat_hw_comp_51_som_control {
	ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE = 0x0,
	ICP_QAT_HW_COMP_51_SOM_CONTROL_DICTIONARY_MODE = 0x1,
	ICP_QAT_HW_COMP_51_SOM_CONTROL_INPUT_CRC = 0x2,
	ICP_QAT_HW_COMP_51_SOM_CONTROL_RESERVED_MODE = 0x3,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS	27
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK		GENMASK(0, 0)
enum icp_qat_hw_comp_51_skip_hash_rd_control {
	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_BITPOS	25
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK	GENMASK(0, 0)
enum icp_qat_hw_comp_51_bypass_compression {
	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED = 0x0,
	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_ENABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS	22
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK	GENMASK(0, 0)
enum icp_qat_hw_comp_51_dmm_algorithm {
	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED = 0x0,
	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_ZSTD_DMM_LITE = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_BITPOS	21
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK	GENMASK(0, 0)
enum icp_qat_hw_comp_51_token_fusion_internal_only {
	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED = 0x0,
	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS	19
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK		GENMASK(1, 0)
enum icp_qat_hw_comp_51_bms {
	ICP_QAT_HW_COMP_51_BMS_BMS_64KB = 0x0,
	ICP_QAT_HW_COMP_51_BMS_BMS_256KB = 0x1,
	ICP_QAT_HW_COMP_51_BMS_BMS_1MB = 0x2,
	ICP_QAT_HW_COMP_51_BMS_BMS_4MB = 0x3,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_BMS_BMS_64KB
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS	18
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK		GENMASK(0, 0)
enum icp_qat_hw_comp_51_scb_mode_reset_mask {
	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT = 0x0,
	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_RESET_HB_HT = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS	2
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK	GENMASK(0, 0)
enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en {
	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_BITPOS	1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK		GENMASK(0, 0)
enum icp_qat_hw_comp_51_cnv_disable {
	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED = 0x0,
	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_DISABLED = 0x1,
};

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_DEFAULT_VAL \
	ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED

Annotation

Immediate include surface: `linux/bits.h`.
Detected declarations: `enum icp_qat_hw_comp_51_som_control`, `enum icp_qat_hw_comp_51_skip_hash_rd_control`, `enum icp_qat_hw_comp_51_bypass_compression`, `enum icp_qat_hw_comp_51_dmm_algorithm`, `enum icp_qat_hw_comp_51_token_fusion_internal_only`, `enum icp_qat_hw_comp_51_bms`, `enum icp_qat_hw_comp_51_scb_mode_reset_mask`, `enum icp_qat_hw_comp_51_zstd_frame_gen_dec_en`, `enum icp_qat_hw_comp_51_cnv_disable`, `enum icp_qat_hw_comp_51_asb_disable`.
Atlas domain: Driver Families / drivers/crypto.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.