drivers/crypto/intel/qat/qat_common/qat_algs.c
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/qat_algs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/qat_algs.c- Extension
.c- Size
- 41065 bytes
- Lines
- 1349
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/slab.hlinux/crypto.hcrypto/internal/aead.hcrypto/internal/cipher.hcrypto/internal/skcipher.hcrypto/aes.hcrypto/sha1.hcrypto/sha2.hcrypto/algapi.hcrypto/authenc.hcrypto/scatterwalk.hcrypto/xts.hlinux/dma-mapping.hadf_accel_devices.hqat_algs_send.hadf_common_drv.hqat_crypto.hicp_qat_hw.hicp_qat_fw.hicp_qat_fw_la.hqat_bl.h
Detected Declarations
struct qat_alg_cdstruct qat_encstruct qat_decstruct qat_alg_aead_ctxstruct qat_alg_skcipher_ctxfunction qat_alg_do_precomputesfunction qat_alg_init_common_hdrfunction qat_alg_aead_init_enc_sessionfunction qat_alg_aead_init_dec_sessionfunction qat_alg_skcipher_init_comfunction qat_alg_skcipher_init_encfunction qat_alg_xts_reverse_keyfunction qat_alg_skcipher_init_decfunction qat_alg_validate_keyfunction qat_alg_aead_init_sessionsfunction qat_alg_skcipher_init_sessionsfunction qat_alg_aead_rekeyfunction qat_alg_aead_newkeyfunction qat_alg_aead_setkeyfunction qat_aead_alg_callbackfunction qat_alg_update_iv_ctr_modefunction qat_alg_update_iv_cbc_modefunction qat_alg_update_ivfunction qat_skcipher_alg_callbackfunction qat_alg_callbackfunction qat_alg_send_sym_messagefunction qat_alg_aead_decfunction qat_alg_aead_encfunction qat_alg_skcipher_rekeyfunction qat_alg_skcipher_newkeyfunction qat_alg_skcipher_setkeyfunction qat_alg_skcipher_cbc_setkeyfunction qat_alg_skcipher_ctr_setkeyfunction qat_alg_skcipher_xts_setkeyfunction qat_alg_set_req_ivfunction qat_alg_skcipher_encryptfunction qat_alg_skcipher_blk_encryptfunction qat_alg_skcipher_xts_encryptfunction qat_alg_skcipher_decryptfunction qat_alg_skcipher_blk_decryptfunction qat_alg_skcipher_xts_decryptfunction qat_alg_aead_initfunction qat_alg_aead_sha1_initfunction qat_alg_aead_sha256_initfunction qat_alg_aead_sha512_initfunction qat_alg_aead_exitfunction qat_alg_skcipher_init_tfmfunction qat_alg_skcipher_init_xts_tfm
Annotated Snippet
struct qat_alg_cd {
union {
struct qat_enc { /* Encrypt content desc */
struct icp_qat_hw_cipher_algo_blk cipher;
struct icp_qat_hw_auth_algo_blk hash;
} qat_enc_cd;
struct qat_dec { /* Decrypt content desc */
struct icp_qat_hw_auth_algo_blk hash;
struct icp_qat_hw_cipher_algo_blk cipher;
} qat_dec_cd;
};
} __aligned(64);
struct qat_alg_aead_ctx {
struct qat_alg_cd *enc_cd;
struct qat_alg_cd *dec_cd;
dma_addr_t enc_cd_paddr;
dma_addr_t dec_cd_paddr;
struct icp_qat_fw_la_bulk_req enc_fw_req;
struct icp_qat_fw_la_bulk_req dec_fw_req;
enum icp_qat_hw_auth_algo qat_hash_alg;
unsigned int hash_digestsize;
unsigned int hash_blocksize;
struct qat_crypto_instance *inst;
};
struct qat_alg_skcipher_ctx {
struct icp_qat_hw_cipher_algo_blk *enc_cd;
struct icp_qat_hw_cipher_algo_blk *dec_cd;
dma_addr_t enc_cd_paddr;
dma_addr_t dec_cd_paddr;
struct icp_qat_fw_la_bulk_req enc_fw_req;
struct icp_qat_fw_la_bulk_req dec_fw_req;
struct qat_crypto_instance *inst;
struct crypto_skcipher *ftfm;
struct crypto_cipher *tweak;
bool fallback;
int mode;
};
static int qat_alg_do_precomputes(struct icp_qat_hw_auth_algo_blk *hash,
struct qat_alg_aead_ctx *ctx,
const u8 *auth_key,
unsigned int auth_keylen)
{
switch (ctx->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1: {
struct hmac_sha1_key key;
__be32 *istate = (__be32 *)hash->sha.state1;
__be32 *ostate = (__be32 *)(hash->sha.state1 +
round_up(sizeof(key.istate.h), 8));
hmac_sha1_preparekey(&key, auth_key, auth_keylen);
for (int i = 0; i < ARRAY_SIZE(key.istate.h); i++) {
istate[i] = cpu_to_be32(key.istate.h[i]);
ostate[i] = cpu_to_be32(key.ostate.h[i]);
}
memzero_explicit(&key, sizeof(key));
return 0;
}
case ICP_QAT_HW_AUTH_ALGO_SHA256: {
struct hmac_sha256_key key;
__be32 *istate = (__be32 *)hash->sha.state1;
__be32 *ostate = (__be32 *)(hash->sha.state1 +
sizeof(key.key.istate.h));
hmac_sha256_preparekey(&key, auth_key, auth_keylen);
for (int i = 0; i < ARRAY_SIZE(key.key.istate.h); i++) {
istate[i] = cpu_to_be32(key.key.istate.h[i]);
ostate[i] = cpu_to_be32(key.key.ostate.h[i]);
}
memzero_explicit(&key, sizeof(key));
return 0;
}
case ICP_QAT_HW_AUTH_ALGO_SHA512: {
struct hmac_sha512_key key;
__be64 *istate = (__be64 *)hash->sha.state1;
__be64 *ostate = (__be64 *)(hash->sha.state1 +
sizeof(key.key.istate.h));
hmac_sha512_preparekey(&key, auth_key, auth_keylen);
for (int i = 0; i < ARRAY_SIZE(key.key.istate.h); i++) {
istate[i] = cpu_to_be64(key.key.istate.h[i]);
ostate[i] = cpu_to_be64(key.key.ostate.h[i]);
}
memzero_explicit(&key, sizeof(key));
return 0;
}
default:
return -EFAULT;
Annotation
- Immediate include surface: `linux/module.h`, `linux/slab.h`, `linux/crypto.h`, `crypto/internal/aead.h`, `crypto/internal/cipher.h`, `crypto/internal/skcipher.h`, `crypto/aes.h`, `crypto/sha1.h`.
- Detected declarations: `struct qat_alg_cd`, `struct qat_enc`, `struct qat_dec`, `struct qat_alg_aead_ctx`, `struct qat_alg_skcipher_ctx`, `function qat_alg_do_precomputes`, `function qat_alg_init_common_hdr`, `function qat_alg_aead_init_enc_session`, `function qat_alg_aead_init_dec_session`, `function qat_alg_skcipher_init_com`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.