drivers/crypto/intel/qat/qat_common/qat_hal.c

Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/qat_hal.c

File Facts

System
Linux kernel
Corpus path
drivers/crypto/intel/qat/qat_common/qat_hal.c
Extension
.c
Size
50945 bytes
Lines
1605
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (times < 0) {
			pr_err("QAT: AE%d is inactive!!\n", ae);
			return -EFAULT;
		}
	}

	return 0;
}

int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
			    unsigned int ae)
{
	unsigned int enable = 0, active = 0;

	enable = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
	active = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);
	if ((enable & (0xff << CE_ENABLE_BITPOS)) ||
	    (active & (1 << ACS_ABO_BITPOS)))
		return 1;
	else
		return 0;
}

static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
{
	unsigned long ae_mask = handle->hal_handle->ae_mask;
	unsigned int misc_ctl_csr, misc_ctl;
	unsigned char ae;

	misc_ctl_csr = handle->chip_info->misc_ctl_csr;
	/* stop the timestamp timers */
	misc_ctl = GET_CAP_CSR(handle, misc_ctl_csr);
	if (misc_ctl & MC_TIMESTAMP_ENABLE)
		SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl &
			    (~MC_TIMESTAMP_ENABLE));

	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);
		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);
	}
	/* start timestamp timers */
	SET_CAP_CSR(handle, misc_ctl_csr, misc_ctl | MC_TIMESTAMP_ENABLE);
}

#define ESRAM_AUTO_TINIT	BIT(2)
#define ESRAM_AUTO_TINIT_DONE	BIT(3)
#define ESRAM_AUTO_INIT_USED_CYCLES (1640)
#define ESRAM_AUTO_INIT_CSR_OFFSET 0xC1C
static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle)
{
	void __iomem *csr_addr =
			(void __iomem *)((uintptr_t)handle->hal_ep_csr_addr_v +
			ESRAM_AUTO_INIT_CSR_OFFSET);
	unsigned int csr_val;
	int times = 30;

	if (handle->pci_dev->device != PCI_DEVICE_ID_INTEL_QAT_DH895XCC)
		return 0;

	csr_val = ADF_CSR_RD(csr_addr, 0);
	if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE))
		return 0;

	csr_val = ADF_CSR_RD(csr_addr, 0);
	csr_val |= ESRAM_AUTO_TINIT;
	ADF_CSR_WR(csr_addr, 0, csr_val);

	do {
		qat_hal_wait_cycles(handle, 0, ESRAM_AUTO_INIT_USED_CYCLES, 0);
		csr_val = ADF_CSR_RD(csr_addr, 0);
	} while (!(csr_val & ESRAM_AUTO_TINIT_DONE) && times--);
	if (times < 0) {
		pr_err("QAT: Fail to init eSram!\n");
		return -EFAULT;
	}
	return 0;
}

#define SHRAM_INIT_CYCLES 2060
int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
{
	unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr;
	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
	unsigned long ae_mask = handle->hal_handle->ae_mask;
	unsigned char ae = 0;
	unsigned int times = 100;
	unsigned int csr_val;

	/* write to the reset csr */

Annotation

Implementation Notes