drivers/crypto/intel/qat/qat_common/qat_uclo.c
Source file repositories/reference/linux-study-clean/drivers/crypto/intel/qat/qat_common/qat_uclo.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/intel/qat/qat_common/qat_uclo.c- Extension
.c- Size
- 67984 bytes
- Lines
- 2292
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/align.hlinux/bitops.hlinux/slab.hlinux/ctype.hlinux/kernel.hlinux/delay.hlinux/pci_ids.hlinux/wordpart.hadf_accel_devices.hadf_anti_rb.hadf_common_drv.hicp_qat_uclo.hicp_qat_hal.hicp_qat_fw_loader_handle.h
Detected Declarations
function qat_uclo_init_ae_datafunction qat_uclo_free_ae_datafunction qat_uclo_check_uof_formatfunction qat_uclo_check_suof_formatfunction qat_uclo_wr_sram_by_wordsfunction qat_uclo_wr_umem_by_wordsfunction qat_uclo_batch_wr_umemfunction qat_uclo_cleanup_batch_init_listfunction qat_uclo_parse_numfunction qat_uclo_fetch_initmem_aefunction qat_uclo_create_batch_init_listfunction qat_uclo_init_lmem_segfunction qat_uclo_init_umem_segfunction qat_uclo_init_ae_memoryfunction qat_uclo_init_ustorefunction for_each_set_bitfunction qat_uclo_init_memoryfunction for_each_set_bitfunction qat_uclo_calc_checksumfunction qat_uclo_calc_str_checksumfunction qat_uclo_map_chunkfunction qat_uclo_check_image_compatfunction qat_uclo_map_image_pagefunction qat_uclo_map_uimagefunction qat_uclo_map_aefunction for_each_set_bitfunction qat_uclo_map_str_tablefunction qat_uclo_map_initmem_tablefunction qat_uclo_get_dev_typefunction qat_uclo_check_uof_compatfunction qat_uclo_init_regfunction qat_uclo_init_reg_symfunction qat_uclo_init_globalsfunction for_each_set_bitfunction qat_hal_set_modesfunction qat_uclo_set_ae_modefunction for_each_set_bitfunction qat_uclo_init_uword_numfunction qat_uclo_parse_uof_objfunction qat_uclo_simg_hdr2sign_lenfunction qat_uclo_simg_hdr2cont_lenfunction qat_uclo_simg_fw_typefunction qat_uclo_map_suof_file_hdrfunction qat_uclo_map_simgfunction qat_uclo_map_suof_symobjsfunction qat_uclo_check_simg_compatfunction qat_uclo_del_suoffunction qat_uclo_tail_img
Annotated Snippet
if (initmem->num_in_bytes) {
if (qat_uclo_init_ae_memory(handle, initmem))
return -EINVAL;
}
initmem = (struct icp_qat_uof_initmem *)((uintptr_t)(
(uintptr_t)initmem +
sizeof(struct icp_qat_uof_initmem)) +
(sizeof(struct icp_qat_uof_memvar_attr) *
initmem->val_attr_num));
}
for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
if (qat_hal_batch_wr_lm(handle, ae,
obj_handle->lm_init_tab[ae])) {
pr_err("fail to batch init lmem for AE %d\n", ae);
return -EINVAL;
}
qat_uclo_cleanup_batch_init_list(handle,
&obj_handle->lm_init_tab[ae]);
qat_uclo_batch_wr_umem(handle, ae,
obj_handle->umem_init_tab[ae]);
qat_uclo_cleanup_batch_init_list(handle,
&obj_handle->
umem_init_tab[ae]);
}
return 0;
}
static void *qat_uclo_find_chunk(struct icp_qat_uof_objhdr *obj_hdr,
char *chunk_id, void *cur)
{
int i;
struct icp_qat_uof_chunkhdr *chunk_hdr =
(struct icp_qat_uof_chunkhdr *)
((uintptr_t)obj_hdr + sizeof(struct icp_qat_uof_objhdr));
for (i = 0; i < obj_hdr->num_chunks; i++) {
if ((cur < (void *)&chunk_hdr[i]) &&
!strncmp(chunk_hdr[i].chunk_id, chunk_id,
ICP_QAT_UOF_OBJID_LEN)) {
return &chunk_hdr[i];
}
}
return NULL;
}
static unsigned int qat_uclo_calc_checksum(unsigned int reg, int ch)
{
int i;
unsigned int topbit = 1 << 0xF;
unsigned int inbyte = (unsigned int)((reg >> 0x18) ^ ch);
reg ^= inbyte << 0x8;
for (i = 0; i < 0x8; i++) {
if (reg & topbit)
reg = (reg << 1) ^ 0x1021;
else
reg <<= 1;
}
return reg & 0xFFFF;
}
static unsigned int qat_uclo_calc_str_checksum(char *ptr, int num)
{
unsigned int chksum = 0;
if (ptr)
while (num--)
chksum = qat_uclo_calc_checksum(chksum, *ptr++);
return chksum;
}
static struct icp_qat_uclo_objhdr *
qat_uclo_map_chunk(char *buf, struct icp_qat_uof_filehdr *file_hdr,
char *chunk_id)
{
struct icp_qat_uof_filechunkhdr *file_chunk;
struct icp_qat_uclo_objhdr *obj_hdr;
char *chunk;
int i;
file_chunk = (struct icp_qat_uof_filechunkhdr *)
(buf + sizeof(struct icp_qat_uof_filehdr));
for (i = 0; i < file_hdr->num_chunks; i++) {
if (!strncmp(file_chunk->chunk_id, chunk_id,
ICP_QAT_UOF_OBJID_LEN)) {
chunk = buf + file_chunk->offset;
if (file_chunk->checksum != qat_uclo_calc_str_checksum(
chunk, file_chunk->size))
break;
Annotation
- Immediate include surface: `linux/align.h`, `linux/bitops.h`, `linux/slab.h`, `linux/ctype.h`, `linux/kernel.h`, `linux/delay.h`, `linux/pci_ids.h`, `linux/wordpart.h`.
- Detected declarations: `function qat_uclo_init_ae_data`, `function qat_uclo_free_ae_data`, `function qat_uclo_check_uof_format`, `function qat_uclo_check_suof_format`, `function qat_uclo_wr_sram_by_words`, `function qat_uclo_wr_umem_by_words`, `function qat_uclo_batch_wr_umem`, `function qat_uclo_cleanup_batch_init_list`, `function qat_uclo_parse_num`, `function qat_uclo_fetch_initmem_ae`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.