drivers/crypto/marvell/cesa/cesa.c
Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/cesa/cesa.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/marvell/cesa/cesa.c- Extension
.c- Size
- 14358 bytes
- Lines
- 581
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/dma-mapping.hlinux/genalloc.hlinux/interrupt.hlinux/io.hlinux/kthread.hlinux/mbus.hlinux/minmax.hlinux/platform_device.hlinux/scatterlist.hlinux/slab.hlinux/module.hlinux/clk.hlinux/of.hlinux/of_platform.hlinux/of_irq.hcesa.h
Detected Declarations
function mv_cesa_dequeue_req_lockedfunction mv_cesa_rearm_enginefunction mv_cesa_std_processfunction mv_cesa_int_processfunction mv_cesa_complete_reqfunction mv_cesa_intfunction mv_cesa_queue_reqfunction mv_cesa_add_algsfunction mv_cesa_remove_algsfunction mv_cesa_conf_mbus_windowsfunction mv_cesa_dev_dma_initfunction mv_cesa_get_sramfunction mv_cesa_put_sramfunction mv_cesa_probefunction mv_cesa_remove
Annotated Snippet
while (true) {
req = mv_cesa_engine_dequeue_complete_request(engine);
if (!req)
break;
ctx = crypto_tfm_ctx(req->tfm);
mv_cesa_complete_req(ctx, req, 0);
}
}
return ret;
}
int mv_cesa_queue_req(struct crypto_async_request *req,
struct mv_cesa_req *creq)
{
int ret;
struct mv_cesa_engine *engine = creq->engine;
spin_lock_bh(&engine->lock);
ret = crypto_enqueue_request(&engine->queue, req);
if ((mv_cesa_req_get_type(creq) == CESA_DMA_REQ) &&
(ret == -EINPROGRESS || ret == -EBUSY))
mv_cesa_tdma_chain(engine, creq);
spin_unlock_bh(&engine->lock);
if (ret != -EINPROGRESS)
return ret;
mv_cesa_rearm_engine(engine);
return -EINPROGRESS;
}
static int mv_cesa_add_algs(struct mv_cesa_dev *cesa)
{
int ret;
int i, j;
for (i = 0; i < cesa->caps->ncipher_algs; i++) {
ret = crypto_register_skcipher(cesa->caps->cipher_algs[i]);
if (ret)
goto err_unregister_crypto;
}
for (i = 0; i < cesa->caps->nahash_algs; i++) {
ret = crypto_register_ahash(cesa->caps->ahash_algs[i]);
if (ret)
goto err_unregister_ahash;
}
return 0;
err_unregister_ahash:
for (j = 0; j < i; j++)
crypto_unregister_ahash(cesa->caps->ahash_algs[j]);
i = cesa->caps->ncipher_algs;
err_unregister_crypto:
for (j = 0; j < i; j++)
crypto_unregister_skcipher(cesa->caps->cipher_algs[j]);
return ret;
}
static void mv_cesa_remove_algs(struct mv_cesa_dev *cesa)
{
int i;
for (i = 0; i < cesa->caps->nahash_algs; i++)
crypto_unregister_ahash(cesa->caps->ahash_algs[i]);
for (i = 0; i < cesa->caps->ncipher_algs; i++)
crypto_unregister_skcipher(cesa->caps->cipher_algs[i]);
}
static struct skcipher_alg *orion_cipher_algs[] = {
&mv_cesa_ecb_des_alg,
&mv_cesa_cbc_des_alg,
&mv_cesa_ecb_des3_ede_alg,
&mv_cesa_cbc_des3_ede_alg,
&mv_cesa_ecb_aes_alg,
&mv_cesa_cbc_aes_alg,
};
static struct ahash_alg *orion_ahash_algs[] = {
&mv_md5_alg,
&mv_sha1_alg,
&mv_ahmac_md5_alg,
&mv_ahmac_sha1_alg,
Annotation
- Immediate include surface: `linux/delay.h`, `linux/dma-mapping.h`, `linux/genalloc.h`, `linux/interrupt.h`, `linux/io.h`, `linux/kthread.h`, `linux/mbus.h`, `linux/minmax.h`.
- Detected declarations: `function mv_cesa_dequeue_req_locked`, `function mv_cesa_rearm_engine`, `function mv_cesa_std_process`, `function mv_cesa_int_process`, `function mv_cesa_complete_req`, `function mv_cesa_int`, `function mv_cesa_queue_req`, `function mv_cesa_add_algs`, `function mv_cesa_remove_algs`, `function mv_cesa_conf_mbus_windows`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.