drivers/crypto/marvell/octeontx/otx_cptvf.h

Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/octeontx/otx_cptvf.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/marvell/octeontx/otx_cptvf.h
Extension
.h
Size
3253 bytes
Lines
105
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct otx_cpt_cmd_chunk {
	u8 *head;
	dma_addr_t dma_addr;
	u32 size; /* Chunk size, max OTX_CPT_INST_CHUNK_MAX_SIZE */
	struct list_head nextchunk;
};

struct otx_cpt_cmd_queue {
	u32 idx;	/* Command queue host write idx */
	u32 num_chunks;	/* Number of command chunks */
	struct otx_cpt_cmd_chunk *qhead;/*
					 * Command queue head, instructions
					 * are inserted here
					 */
	struct otx_cpt_cmd_chunk *base;
	struct list_head chead;
};

struct otx_cpt_cmd_qinfo {
	u32 qchunksize; /* Command queue chunk size */
	struct otx_cpt_cmd_queue queue[OTX_CPT_NUM_QS_PER_VF];
};

struct otx_cpt_pending_qinfo {
	u32 num_queues;	/* Number of queues supported */
	struct otx_cpt_pending_queue queue[OTX_CPT_NUM_QS_PER_VF];
};

#define for_each_pending_queue(qinfo, q, i)	\
		for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \
		     q = &qinfo->queue[i])

struct otx_cptvf_wqe {
	struct tasklet_struct twork;
	struct otx_cptvf *cptvf;
};

struct otx_cptvf_wqe_info {
	struct otx_cptvf_wqe vq_wqe[OTX_CPT_NUM_QS_PER_VF];
};

struct otx_cptvf {
	u16 flags;	/* Flags to hold device status bits */
	u8 vfid;	/* Device Index 0...OTX_CPT_MAX_VF_NUM */
	u8 num_vfs;	/* Number of enabled VFs */
	u8 vftype;	/* VF type of SE_TYPE(2) or AE_TYPE(1) */
	u8 vfgrp;	/* VF group (0 - 8) */
	u8 node;	/* Operating node: Bits (46:44) in BAR0 address */
	u8 priority;	/*
			 * VF priority ring: 1-High proirity round
			 * robin ring;0-Low priority round robin ring;
			 */
	struct pci_dev *pdev;	/* Pci device handle */
	void __iomem *reg_base;	/* Register start address */
	void *wqe_info;		/* BH worker info */
	/* MSI-X */
	cpumask_var_t affinity_mask[OTX_CPT_VF_MSIX_VECTORS];
	/* Command and Pending queues */
	u32 qsize;
	u32 num_queues;
	struct otx_cpt_cmd_qinfo cqinfo; /* Command queue information */
	struct otx_cpt_pending_qinfo pqinfo; /* Pending queue information */
	/* VF-PF mailbox communication */
	bool pf_acked;
	bool pf_nacked;
};

int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf);
int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf);
int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group);
int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf);
int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf);
int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf);
void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf);
void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val);

#endif /* __OTX_CPTVF_H */

Annotation

Implementation Notes