drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h

Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
Extension
.h
Size
13376 bytes
Lines
484
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cn9k_cpt_res_s {
		u64 compcode:8;
		u64 uc_compcode:8;
		u64 doneint:1;
		u64 reserved_17_63:47;
		u64 reserved_64_127;
	} s;

	struct cn10k_cpt_res_s {
		u64 compcode:7;
		u64 doneint:1;
		u64 uc_compcode:8;
		u64 rlen:16;
		u64 spi:32;
		u64 esn;
	} cn10k;
};

/*
 * Register (RVU_PF_BAR0) cpt#_af_constants1
 *
 * CPT AF Constants Register
 * This register contains implementation-related parameters of CPT.
 */
union otx2_cptx_af_constants1 {
	u64 u;
	struct otx2_cptx_af_constants1_s {
		u64 se:16;
		u64 ie:16;
		u64 ae:16;
		u64 reserved_48_63:16;
	} s;
};

/*
 * RVU_PFVF_BAR2 - cpt_lf_misc_int
 *
 * This register contain the per-queue miscellaneous interrupts.
 *
 */
union otx2_cptx_lf_misc_int {
	u64 u;
	struct otx2_cptx_lf_misc_int_s {
		u64 reserved_0:1;
		u64 nqerr:1;
		u64 irde:1;
		u64 nwrp:1;
		u64 reserved_4:1;
		u64 hwerr:1;
		u64 fault:1;
		u64 reserved_7_63:57;
	} s;
};

/*
 * RVU_PFVF_BAR2 - cpt_lf_misc_int_ena_w1s
 *
 * This register sets interrupt enable bits.
 *
 */
union otx2_cptx_lf_misc_int_ena_w1s {
	u64 u;
	struct otx2_cptx_lf_misc_int_ena_w1s_s {
		u64 reserved_0:1;
		u64 nqerr:1;
		u64 irde:1;
		u64 nwrp:1;
		u64 reserved_4:1;
		u64 hwerr:1;
		u64 fault:1;
		u64 reserved_7_63:57;
	} s;
};

/*
 * RVU_PFVF_BAR2 - cpt_lf_ctl
 *
 * This register configures the queue.
 *
 * When the queue is not execution-quiescent (see CPT_LF_INPROG[EENA,INFLIGHT]),
 * software must only write this register with [ENA]=0.
 */
union otx2_cptx_lf_ctl {
	u64 u;
	struct otx2_cptx_lf_ctl_s {
		u64 ena:1;
		u64 fc_ena:1;
		u64 fc_up_crossing:1;
		u64 reserved_3:1;
		u64 fc_hyst_bits:4;

Annotation

Implementation Notes