drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h- Extension
.h- Size
- 15393 bytes
- Lines
- 562
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
otx2_cpt_common.h
Detected Declarations
struct otx2_cptvf_requeststruct otx2_cpt_iq_commandstruct otx2_cpt_pending_entrystruct otx2_cpt_pending_queuestruct otx2_cpt_buf_ptrstruct otx2_cpt_req_infostruct otx2_cpt_inst_infostruct otx2_cpt_sglist_componentstruct cn10kb_cpt_sglist_componentstruct otx2_cptlf_wqefunction otx2_cpt_info_destroyfunction setup_sgio_componentsfunction sgv2io_components_setupfunction cn10k_sgv2_info_createfunction otx2_sg_info_create
Annotated Snippet
struct otx2_cptvf_request {
u32 param1;
u32 param2;
u16 dlen;
union otx2_cpt_opcode opcode;
dma_addr_t cptr_dma;
void *cptr;
};
/*
* CPT_INST_S software command definitions
* Words EI (0-3)
*/
union otx2_cpt_iq_cmd_word0 {
u64 u;
struct {
__be16 opcode;
__be16 param1;
__be16 param2;
__be16 dlen;
} s;
};
union otx2_cpt_iq_cmd_word3 {
u64 u;
struct {
u64 cptr:61;
u64 grp:3;
} s;
};
struct otx2_cpt_iq_command {
union otx2_cpt_iq_cmd_word0 cmd;
u64 dptr;
u64 rptr;
union otx2_cpt_iq_cmd_word3 cptr;
};
struct otx2_cpt_pending_entry {
void *completion_addr; /* Completion address */
void *info;
/* Kernel async request callback */
void (*callback)(int status, void *arg1, void *arg2);
struct crypto_async_request *areq; /* Async request callback arg */
u8 resume_sender; /* Notify sender to resume sending requests */
u8 busy; /* Entry status (free/busy) */
};
struct otx2_cpt_pending_queue {
struct otx2_cpt_pending_entry *head; /* Head of the queue */
u32 front; /* Process work from here */
u32 rear; /* Append new work here */
u32 pending_count; /* Pending requests count */
u32 qlen; /* Queue length */
spinlock_t lock; /* Queue lock */
};
struct otx2_cpt_buf_ptr {
u8 *vptr;
dma_addr_t dma_addr;
u16 size;
};
union otx2_cpt_ctrl_info {
u32 flags;
struct {
#if defined(__BIG_ENDIAN_BITFIELD)
u32 reserved_6_31:26;
u32 grp:3; /* Group bits */
u32 dma_mode:2; /* DMA mode */
u32 se_req:1; /* To SE core */
#else
u32 se_req:1; /* To SE core */
u32 dma_mode:2; /* DMA mode */
u32 grp:3; /* Group bits */
u32 reserved_6_31:26;
#endif
} s;
};
struct otx2_cpt_req_info {
/* Kernel async request callback */
void (*callback)(int status, void *arg1, void *arg2);
struct crypto_async_request *areq; /* Async request callback arg */
struct otx2_cptvf_request req;/* Request information (core specific) */
union otx2_cpt_ctrl_info ctrl;/* User control information */
struct otx2_cpt_buf_ptr in[OTX2_CPT_MAX_SG_IN_CNT];
struct otx2_cpt_buf_ptr out[OTX2_CPT_MAX_SG_OUT_CNT];
u8 *iv_out; /* IV to send back */
u16 rlen; /* Output length */
Annotation
- Immediate include surface: `otx2_cpt_common.h`.
- Detected declarations: `struct otx2_cptvf_request`, `struct otx2_cpt_iq_command`, `struct otx2_cpt_pending_entry`, `struct otx2_cpt_pending_queue`, `struct otx2_cpt_buf_ptr`, `struct otx2_cpt_req_info`, `struct otx2_cpt_inst_info`, `struct otx2_cpt_sglist_component`, `struct cn10kb_cpt_sglist_component`, `struct otx2_cptlf_wqe`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.