drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h

Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h

File Facts

System
Linux kernel
Corpus path
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
Extension
.h
Size
5267 bytes
Lines
173
Domain
Driver Families
Bucket
drivers/crypto
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct otx2_cpt_bitmap {
	unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN];
	int size;
};

struct otx2_cpt_engines {
	int type;
	int count;
};

/* Microcode version number */
struct otx2_cpt_ucode_ver_num {
	u8 nn;
	u8 xx;
	u8 yy;
	u8 zz;
};

struct otx2_cpt_ucode_hdr {
	struct otx2_cpt_ucode_ver_num ver_num;
	u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];
	__be32 code_length;
	u32 padding[3];
};

struct otx2_cpt_ucode {
	u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ + 1];/*
					       * ucode version in readable
					       * format
					       */
	struct otx2_cpt_ucode_ver_num ver_num;/* ucode version number */
	char filename[OTX2_CPT_NAME_LENGTH];/* ucode filename */
	dma_addr_t dma;		/* phys address of ucode image */
	void *va;		/* virt address of ucode image */
	u32 size;		/* ucode image size */
	int type;		/* ucode image type SE, IE, AE or SE+IE */
};

struct otx2_cpt_uc_info_t {
	struct list_head list;
	struct otx2_cpt_ucode ucode;/* microcode information */
	const struct firmware *fw;
};

/* Maximum and current number of engines available for all engine groups */
struct otx2_cpt_engs_available {
	int max_se_cnt;
	int max_ie_cnt;
	int max_ae_cnt;
	int se_cnt;
	int ie_cnt;
	int ae_cnt;
};

/* Engines reserved to an engine group */
struct otx2_cpt_engs_rsvd {
	int type;	/* engine type */
	int count;	/* number of engines attached */
	int offset;     /* constant offset of engine type in the bitmap */
	unsigned long *bmap;		/* attached engines bitmap */
	struct otx2_cpt_ucode *ucode;	/* ucode used by these engines */
};

struct otx2_cpt_mirror_info {
	int is_ena;	/*
			 * is mirroring enabled, it is set only for engine
			 * group which mirrors another engine group
			 */
	int idx;	/*
			 * index of engine group which is mirrored by this
			 * group, set only for engine group which mirrors
			 * another group
			 */
	int ref_count;	/*
			 * number of times this engine group is mirrored by
			 * other groups, this is set only for engine group
			 * which is mirrored by other group(s)
			 */
};

struct otx2_cpt_eng_grp_info {
	struct otx2_cpt_eng_grps *g; /* pointer to engine_groups structure */
	/* engines attached */
	struct otx2_cpt_engs_rsvd engs[OTX2_CPT_MAX_ETYPES_PER_GRP];
	/* ucodes information */
	struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP];
	/* engine group mirroring information */
	struct otx2_cpt_mirror_info mirror;
	int idx;	 /* engine group index */
	bool is_enabled; /*

Annotation

Implementation Notes