drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
Source file repositories/reference/linux-study-clean/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c- Extension
.c- Size
- 6885 bytes
- Lines
- 242
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
otx2_cpt_common.hotx2_cptvf.hrvu_reg.h
Detected Declarations
function otx2_cpt_mbox_bbuf_initfunction otx2_cpt_sync_mbox_bbuffunction otx2_cptvf_pfvf_mbox_intrfunction process_pfvf_mbox_mbox_msgfunction otx2_cptvf_pfvf_mbox_handlerfunction otx2_cptvf_send_eng_grp_num_msgfunction otx2_cptvf_send_kvf_limits_msgfunction otx2_cptvf_send_caps_msg
Annotated Snippet
if (msg->rc) {
dev_err(&cptvf->pdev->dev,
"Reg %llx rd/wr(%d) failed %d\n",
rsp_reg->reg_offset, rsp_reg->is_write,
msg->rc);
return;
}
if (!rsp_reg->is_write)
*rsp_reg->ret_val = rsp_reg->val;
break;
case MBOX_MSG_GET_ENG_GRP_NUM:
rsp_grp = (struct otx2_cpt_egrp_num_rsp *) msg;
grp_num = rsp_grp->eng_grp_num;
if (rsp_grp->eng_type == OTX2_CPT_SE_TYPES)
cptvf->lfs.kcrypto_se_eng_grp_num = grp_num;
else if (rsp_grp->eng_type == OTX2_CPT_AE_TYPES)
cptvf->lfs.kcrypto_ae_eng_grp_num = grp_num;
break;
case MBOX_MSG_GET_KVF_LIMITS:
rsp_limits = (struct otx2_cpt_kvf_limits_rsp *) msg;
cptvf->lfs.kvf_limits = rsp_limits->kvf_limits;
break;
case MBOX_MSG_GET_CAPS:
eng_caps = (struct otx2_cpt_caps_rsp *)msg;
memcpy(cptvf->eng_caps, eng_caps->eng_caps,
sizeof(cptvf->eng_caps));
break;
case MBOX_MSG_CPT_LF_RESET:
case MBOX_MSG_LMTST_TBL_SETUP:
break;
default:
dev_err(&cptvf->pdev->dev, "Unsupported msg %d received.\n",
msg->id);
break;
}
}
void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work)
{
struct otx2_cptvf_dev *cptvf;
struct otx2_mbox *pfvf_mbox;
struct otx2_mbox_dev *mdev;
struct mbox_hdr *rsp_hdr;
struct mbox_msghdr *msg;
int offset, i;
/* sync with mbox memory region */
smp_rmb();
cptvf = container_of(work, struct otx2_cptvf_dev, pfvf_mbox_work);
pfvf_mbox = &cptvf->pfvf_mbox;
otx2_cpt_sync_mbox_bbuf(pfvf_mbox, 0);
mdev = &pfvf_mbox->dev[0];
rsp_hdr = (struct mbox_hdr *)(mdev->mbase + pfvf_mbox->rx_start);
if (rsp_hdr->num_msgs == 0)
return;
offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
for (i = 0; i < rsp_hdr->num_msgs; i++) {
msg = (struct mbox_msghdr *)(mdev->mbase + pfvf_mbox->rx_start +
offset);
process_pfvf_mbox_mbox_msg(cptvf, msg);
offset = msg->next_msgoff;
mdev->msgs_acked++;
}
otx2_mbox_reset(pfvf_mbox, 0);
}
int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type)
{
struct otx2_mbox *mbox = &cptvf->pfvf_mbox;
struct pci_dev *pdev = cptvf->pdev;
struct otx2_cpt_egrp_num_msg *req;
req = (struct otx2_cpt_egrp_num_msg *)
otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
sizeof(struct otx2_cpt_egrp_num_rsp));
if (req == NULL) {
dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
return -EFAULT;
}
req->hdr.id = MBOX_MSG_GET_ENG_GRP_NUM;
req->hdr.sig = OTX2_MBOX_REQ_SIG;
req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptvf->pdev, cptvf->vf_id, 0);
req->eng_type = eng_type;
return otx2_cpt_send_mbox_msg(mbox, pdev);
}
int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf)
Annotation
- Immediate include surface: `otx2_cpt_common.h`, `otx2_cptvf.h`, `rvu_reg.h`.
- Detected declarations: `function otx2_cpt_mbox_bbuf_init`, `function otx2_cpt_sync_mbox_bbuf`, `function otx2_cptvf_pfvf_mbox_intr`, `function process_pfvf_mbox_mbox_msg`, `function otx2_cptvf_pfvf_mbox_handler`, `function otx2_cptvf_send_eng_grp_num_msg`, `function otx2_cptvf_send_kvf_limits_msg`, `function otx2_cptvf_send_caps_msg`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.