drivers/crypto/mxs-dcp.c
Source file repositories/reference/linux-study-clean/drivers/crypto/mxs-dcp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/mxs-dcp.c- Extension
.c- Size
- 32135 bytes
- Lines
- 1263
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/interrupt.hlinux/io.hlinux/kernel.hlinux/kthread.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/stmp_device.hlinux/clk.hsoc/fsl/dcp.hcrypto/aes.hcrypto/sha1.hcrypto/sha2.hcrypto/internal/hash.hcrypto/internal/skcipher.hcrypto/scatterwalk.h
Detected Declarations
struct dcp_dma_descstruct dcp_coherent_blockstruct dcpstruct dcp_async_ctxstruct dcp_aes_req_ctxstruct dcp_sha_req_ctxstruct dcp_export_stateenum dcp_chanfunction mxs_dcp_start_dmafunction Encryptionfunction mxs_dcp_aes_block_cryptfunction for_each_sgfunction dcp_chan_thread_aesfunction mxs_dcp_block_fallbackfunction mxs_dcp_aes_enqueuefunction mxs_dcp_aes_ecb_decryptfunction mxs_dcp_aes_ecb_encryptfunction mxs_dcp_aes_cbc_decryptfunction mxs_dcp_aes_cbc_encryptfunction mxs_dcp_aes_setkeyfunction mxs_dcp_aes_setrefkeyfunction mxs_dcp_aes_fallback_init_tfmfunction mxs_dcp_aes_fallback_exit_tfmfunction mxs_dcp_paes_init_tfmfunction Hashingfunction dcp_sha_req_to_buffunction dcp_chan_thread_shafunction dcp_sha_initfunction dcp_sha_update_fxfunction dcp_sha_updatefunction dcp_sha_finalfunction dcp_sha_finupfunction dcp_sha_digestfunction dcp_sha_importfunction dcp_sha_exportfunction dcp_sha_cra_initfunction dcp_sha_cra_exitfunction mxs_dcp_irqfunction mxs_dcp_probefunction mxs_dcp_remove
Annotated Snippet
struct dcp_dma_desc {
uint32_t next_cmd_addr;
uint32_t control0;
uint32_t control1;
uint32_t source;
uint32_t destination;
uint32_t size;
uint32_t payload;
uint32_t status;
};
/* Coherent aligned block for bounce buffering. */
struct dcp_coherent_block {
uint8_t aes_in_buf[DCP_BUF_SZ];
uint8_t aes_out_buf[DCP_BUF_SZ];
uint8_t sha_in_buf[DCP_BUF_SZ];
uint8_t sha_out_buf[DCP_SHA_PAY_SZ];
uint8_t aes_key[2 * AES_KEYSIZE_128];
struct dcp_dma_desc desc[DCP_MAX_CHANS];
};
struct dcp {
struct device *dev;
void __iomem *base;
uint32_t caps;
struct dcp_coherent_block *coh;
struct completion completion[DCP_MAX_CHANS];
spinlock_t lock[DCP_MAX_CHANS];
struct task_struct *thread[DCP_MAX_CHANS];
struct crypto_queue queue[DCP_MAX_CHANS];
struct clk *dcp_clk;
};
enum dcp_chan {
DCP_CHAN_HASH_SHA = 0,
DCP_CHAN_CRYPTO = 2,
};
struct dcp_async_ctx {
/* Common context */
enum dcp_chan chan;
uint32_t fill;
/* SHA Hash-specific context */
struct mutex mutex;
uint32_t alg;
unsigned int hot:1;
/* Crypto-specific context */
struct crypto_skcipher *fallback;
unsigned int key_len;
uint8_t key[AES_KEYSIZE_128];
bool key_referenced;
};
struct dcp_aes_req_ctx {
unsigned int enc:1;
unsigned int ecb:1;
struct skcipher_request fallback_req; // keep at the end
};
struct dcp_sha_req_ctx {
unsigned int init:1;
unsigned int fini:1;
};
struct dcp_export_state {
struct dcp_sha_req_ctx req_ctx;
struct dcp_async_ctx async_ctx;
};
/*
* There can even be only one instance of the MXS DCP due to the
* design of Linux Crypto API.
*/
static struct dcp *global_sdcp;
/* DCP register layout. */
#define MXS_DCP_CTRL 0x00
#define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
#define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
#define MXS_DCP_STAT 0x10
#define MXS_DCP_STAT_CLR 0x18
#define MXS_DCP_STAT_IRQ_MASK 0xf
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/interrupt.h`, `linux/io.h`, `linux/kernel.h`, `linux/kthread.h`, `linux/module.h`, `linux/of.h`, `linux/platform_device.h`.
- Detected declarations: `struct dcp_dma_desc`, `struct dcp_coherent_block`, `struct dcp`, `struct dcp_async_ctx`, `struct dcp_aes_req_ctx`, `struct dcp_sha_req_ctx`, `struct dcp_export_state`, `enum dcp_chan`, `function mxs_dcp_start_dma`, `function Encryption`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.