drivers/crypto/qce/aead.c
Source file repositories/reference/linux-study-clean/drivers/crypto/qce/aead.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/qce/aead.c- Extension
.c- Size
- 23709 bytes
- Lines
- 842
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/interrupt.hlinux/string.hcrypto/gcm.hcrypto/authenc.hcrypto/internal/aead.hcrypto/internal/des.hcrypto/sha1.hcrypto/sha2.hcrypto/scatterwalk.haead.h
Detected Declarations
struct qce_aead_deffunction qce_aead_donefunction qce_aead_prepare_result_buffunction qce_aead_prepare_ccm_result_buffunction qce_aead_prepare_dst_buffunction qce_aead_ccm_prepare_buf_assoclenfunction datafunction qce_aead_prepare_buffunction qce_aead_ccm_prepare_buffunction qce_aead_create_ccm_noncefunction qce_aead_async_req_handlefunction qce_aead_cryptfunction qce_aead_encryptfunction qce_aead_decryptfunction qce_aead_ccm_setkeyfunction qce_aead_setkeyfunction qce_aead_setauthsizefunction qce_aead_initfunction qce_aead_exitfunction qce_aead_register_onefunction qce_aead_unregisterfunction list_for_each_entry_safefunction qce_aead_register
Annotated Snippet
struct qce_aead_def {
unsigned long flags;
const char *name;
const char *drv_name;
unsigned int blocksize;
unsigned int chunksize;
unsigned int ivsize;
unsigned int maxauthsize;
};
static const struct qce_aead_def aead_def[] = {
{
.flags = QCE_ALG_DES | QCE_MODE_CBC | QCE_HASH_SHA1_HMAC,
.name = "authenc(hmac(sha1),cbc(des))",
.drv_name = "authenc-hmac-sha1-cbc-des-qce",
.blocksize = DES_BLOCK_SIZE,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
{
.flags = QCE_ALG_3DES | QCE_MODE_CBC | QCE_HASH_SHA1_HMAC,
.name = "authenc(hmac(sha1),cbc(des3_ede))",
.drv_name = "authenc-hmac-sha1-cbc-3des-qce",
.blocksize = DES3_EDE_BLOCK_SIZE,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA1_DIGEST_SIZE,
},
{
.flags = QCE_ALG_DES | QCE_MODE_CBC | QCE_HASH_SHA256_HMAC,
.name = "authenc(hmac(sha256),cbc(des))",
.drv_name = "authenc-hmac-sha256-cbc-des-qce",
.blocksize = DES_BLOCK_SIZE,
.ivsize = DES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
{
.flags = QCE_ALG_3DES | QCE_MODE_CBC | QCE_HASH_SHA256_HMAC,
.name = "authenc(hmac(sha256),cbc(des3_ede))",
.drv_name = "authenc-hmac-sha256-cbc-3des-qce",
.blocksize = DES3_EDE_BLOCK_SIZE,
.ivsize = DES3_EDE_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
{
.flags = QCE_ALG_AES | QCE_MODE_CBC | QCE_HASH_SHA256_HMAC,
.name = "authenc(hmac(sha256),cbc(aes))",
.drv_name = "authenc-hmac-sha256-cbc-aes-qce",
.blocksize = AES_BLOCK_SIZE,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = SHA256_DIGEST_SIZE,
},
{
.flags = QCE_ALG_AES | QCE_MODE_CCM,
.name = "ccm(aes)",
.drv_name = "ccm-aes-qce",
.blocksize = 1,
.ivsize = AES_BLOCK_SIZE,
.maxauthsize = AES_BLOCK_SIZE,
},
{
.flags = QCE_ALG_AES | QCE_MODE_CCM | QCE_MODE_CCM_RFC4309,
.name = "rfc4309(ccm(aes))",
.drv_name = "rfc4309-ccm-aes-qce",
.blocksize = 1,
.ivsize = 8,
.maxauthsize = AES_BLOCK_SIZE,
},
};
static int qce_aead_register_one(const struct qce_aead_def *def, struct qce_device *qce)
{
struct qce_alg_template *tmpl;
struct aead_alg *alg;
int ret;
tmpl = kzalloc_obj(*tmpl);
if (!tmpl)
return -ENOMEM;
alg = &tmpl->alg.aead;
strscpy(alg->base.cra_name, def->name);
strscpy(alg->base.cra_driver_name, def->drv_name);
alg->base.cra_blocksize = def->blocksize;
alg->chunksize = def->chunksize;
alg->ivsize = def->ivsize;
alg->maxauthsize = def->maxauthsize;
if (IS_CCM(def->flags))
alg->setkey = qce_aead_ccm_setkey;
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/interrupt.h`, `linux/string.h`, `crypto/gcm.h`, `crypto/authenc.h`, `crypto/internal/aead.h`, `crypto/internal/des.h`, `crypto/sha1.h`.
- Detected declarations: `struct qce_aead_def`, `function qce_aead_done`, `function qce_aead_prepare_result_buf`, `function qce_aead_prepare_ccm_result_buf`, `function qce_aead_prepare_dst_buf`, `function qce_aead_ccm_prepare_buf_assoclen`, `function data`, `function qce_aead_prepare_buf`, `function qce_aead_ccm_prepare_buf`, `function qce_aead_create_ccm_nonce`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.