drivers/crypto/stm32/stm32-hash.c
Source file repositories/reference/linux-study-clean/drivers/crypto/stm32/stm32-hash.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/crypto/stm32/stm32-hash.c- Extension
.c- Size
- 63416 bytes
- Lines
- 2539
- Domain
- Driver Families
- Bucket
- drivers/crypto
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
crypto/engine.hcrypto/internal/hash.hcrypto/md5.hcrypto/scatterwalk.hcrypto/sha1.hcrypto/sha2.hcrypto/sha3.hlinux/clk.hlinux/delay.hlinux/dma-mapping.hlinux/dmaengine.hlinux/interrupt.hlinux/iopoll.hlinux/kernel.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/reset.hlinux/string.h
Detected Declarations
struct stm32_hash_ctxstruct stm32_hash_statestruct stm32_hash_request_ctxstruct stm32_hash_algs_infostruct stm32_hash_pdatastruct stm32_hash_devstruct stm32_hash_drvenum stm32_hash_data_formatenum stm32_hash_algoenum ux500_hash_algofunction stm32_hash_readfunction stm32_hash_writefunction stm32_hash_wait_busyfunction stm32_hash_set_nblwfunction stm32_hash_write_keyfunction stm32_hash_write_ctrlfunction stm32_hash_append_sgfunction stm32_hash_xmit_cpufunction hash_swap_regfunction stm32_hash_update_cpufunction stm32_hash_xmit_dmafunction stm32_hash_dma_callbackfunction stm32_hash_hmac_dma_sendfunction stm32_hash_dma_initfunction stm32_hash_dma_sendfunction for_each_sgfunction bitfunction stm32_hash_initfunction stm32_hash_update_reqfunction stm32_hash_final_reqfunction stm32_hash_emptymsg_fallbackfunction stm32_hash_copy_hashfunction stm32_hash_finishfunction stm32_hash_finish_reqfunction stm32_hash_handle_queuefunction stm32_hash_one_requestfunction stm32_hash_copy_sgsfunction stm32_hash_align_sgsfunction stm32_hash_prepare_requestfunction stm32_hash_unprepare_requestfunction stm32_hash_enqueuefunction stm32_hash_updatefunction stm32_hash_finalfunction stm32_hash_finupfunction stm32_hash_digestfunction stm32_hash_exportfunction stm32_hash_importfunction stm32_hash_setkey
Annotated Snippet
struct stm32_hash_ctx {
struct stm32_hash_dev *hdev;
struct crypto_shash *xtfm;
unsigned long flags;
u8 key[HASH_MAX_KEY_SIZE];
int keylen;
};
struct stm32_hash_state {
u32 flags;
u16 bufcnt;
u16 blocklen;
u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
/* hash state */
u32 hw_context[3 + HASH_CSR_NB_MAX];
};
struct stm32_hash_request_ctx {
struct stm32_hash_dev *hdev;
unsigned long op;
u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
size_t digcnt;
struct scatterlist *sg;
struct scatterlist sgl[2]; /* scatterlist used to realize alignment */
unsigned int offset;
unsigned int total;
struct scatterlist sg_key;
dma_addr_t dma_addr;
size_t dma_ct;
int nents;
u8 data_type;
struct stm32_hash_state state;
};
struct stm32_hash_algs_info {
struct ahash_engine_alg *algs_list;
size_t size;
};
struct stm32_hash_pdata {
const int alg_shift;
const struct stm32_hash_algs_info *algs_info;
size_t algs_info_size;
bool has_sr;
bool has_mdmat;
bool context_secured;
bool broken_emptymsg;
bool ux500;
};
struct stm32_hash_dev {
struct list_head list;
struct device *dev;
struct clk *clk;
struct reset_control *rst;
void __iomem *io_base;
phys_addr_t phys_base;
u8 xmit_buf[HASH_BUFLEN] __aligned(sizeof(u32));
u32 dma_mode;
bool polled;
struct ahash_request *req;
struct crypto_engine *engine;
unsigned long flags;
struct dma_chan *dma_lch;
struct completion dma_completion;
const struct stm32_hash_pdata *pdata;
};
struct stm32_hash_drv {
struct list_head dev_list;
spinlock_t lock; /* List protection access */
};
static struct stm32_hash_drv stm32_hash = {
.dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
.lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
};
Annotation
- Immediate include surface: `crypto/engine.h`, `crypto/internal/hash.h`, `crypto/md5.h`, `crypto/scatterwalk.h`, `crypto/sha1.h`, `crypto/sha2.h`, `crypto/sha3.h`, `linux/clk.h`.
- Detected declarations: `struct stm32_hash_ctx`, `struct stm32_hash_state`, `struct stm32_hash_request_ctx`, `struct stm32_hash_algs_info`, `struct stm32_hash_pdata`, `struct stm32_hash_dev`, `struct stm32_hash_drv`, `enum stm32_hash_data_format`, `enum stm32_hash_algo`, `enum ux500_hash_algo`.
- Atlas domain: Driver Families / drivers/crypto.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.