drivers/crypto/ti/Kconfig

File Facts

System

Linux kernel

Corpus path

drivers/crypto/ti/Kconfig

Extension

[no extension]

Size

611 bytes

Lines

20

Domain

Driver Families

Bucket

drivers/crypto

Inferred role

Driver Families: build/configuration rule

Status

atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
config CRYPTO_DEV_TI_DTHEV2
	tristate "Support for TI DTHE V2 cryptography engine"
	depends on ARCH_K3 || COMPILE_TEST
	select CRYPTO_ENGINE
	select CRYPTO_SKCIPHER
	select CRYPTO_ECB
	select CRYPTO_CBC
	select CRYPTO_CTR
	select CRYPTO_XTS
	select CRYPTO_GCM
	select CRYPTO_CCM
	select SG_SPLIT
	help
	  This enables support for the TI DTHE V2 hw cryptography engine
	  which can be found on TI K3 SOCs. Selecting this enables use
	  of hardware offloading for cryptographic algorithms on
	  these devices, providing enhanced resistance against side-channel
	  attacks.

Annotation

• Atlas domain: Driver Families / drivers/crypto.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.