drivers/cxl/core/port.c
Source file repositories/reference/linux-study-clean/drivers/cxl/core/port.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/cxl/core/port.c- Extension
.c- Size
- 64687 bytes
- Lines
- 2566
- Domain
- Driver Families
- Bucket
- drivers/cxl
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/platform_device.hlinux/memregion.hlinux/workqueue.hlinux/debugfs.hlinux/device.hlinux/module.hlinux/pci.hlinux/slab.hlinux/idr.hlinux/node.hcxl/einj.hcxlmem.hcxlpci.hcxl.hcore.h
Detected Declarations
struct cxl_find_port_ctxstruct detach_ctxfunction devicesfunction cxl_num_decoders_committedfunction devtype_showfunction cxl_device_idfunction modalias_showfunction start_showfunction size_showfunction target_type_showfunction emit_target_listfunction target_list_showfunction mode_showfunction mode_storefunction dpa_resource_showfunction dpa_size_showfunction dpa_size_storefunction interleave_granularity_showfunction interleave_ways_showfunction qos_class_showfunction can_create_pmemfunction can_create_ramfunction cxl_root_decoder_visiblefunction __cxl_decoder_releasefunction cxl_endpoint_decoder_releasefunction cxl_switch_decoder_releasefunction cxl_root_decoder_releasefunction is_endpoint_decoderfunction is_root_decoderfunction is_switch_decoderfunction cxl_ep_releasefunction cxl_ep_removefunction cxl_port_releasefunction decoders_committed_showfunction is_cxl_portfunction unregister_portfunction cxl_unlink_uportfunction devm_cxl_link_uportfunction cxl_unlink_parent_dportfunction devm_cxl_link_parent_dportfunction cxl_setup_comp_regsfunction cxl_port_setup_regsfunction cxl_dport_setup_regsfunction cxl_einj_injectfunction cxl_debugfs_create_dport_dirfunction cxl_port_addfunction unregister_pci_busfunction devm_cxl_register_pci_bus
Annotated Snippet
static int cxl_bus_match(struct device *dev, const struct device_driver *drv)
{
return cxl_device_id(dev) == to_cxl_drv(drv)->id;
}
static int cxl_bus_probe(struct device *dev)
{
int rc;
rc = to_cxl_drv(dev->driver)->probe(dev);
dev_dbg(dev, "probe: %d\n", rc);
return rc;
}
static void cxl_bus_remove(struct device *dev)
{
struct cxl_driver *cxl_drv = to_cxl_drv(dev->driver);
if (cxl_drv->remove)
cxl_drv->remove(dev);
}
static struct workqueue_struct *cxl_bus_wq;
static int cxl_rescan_attach(struct device *dev, void *data)
{
int rc = device_attach(dev);
dev_vdbg(dev, "rescan: %s\n", rc ? "attach" : "detached");
return 0;
}
static void cxl_bus_rescan_queue(struct work_struct *w)
{
bus_for_each_dev(&cxl_bus_type, NULL, NULL, cxl_rescan_attach);
}
void cxl_bus_rescan(void)
{
static DECLARE_WORK(rescan_work, cxl_bus_rescan_queue);
queue_work(cxl_bus_wq, &rescan_work);
}
EXPORT_SYMBOL_NS_GPL(cxl_bus_rescan, "CXL");
void cxl_bus_drain(void)
{
drain_workqueue(cxl_bus_wq);
}
EXPORT_SYMBOL_NS_GPL(cxl_bus_drain, "CXL");
bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
{
return queue_work(cxl_bus_wq, &cxlmd->detach_work);
}
EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, "CXL");
static void add_latency(struct access_coordinate *c, long latency)
{
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
c[i].write_latency += latency;
c[i].read_latency += latency;
}
}
static bool coordinates_valid(struct access_coordinate *c)
{
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
if (c[i].read_bandwidth && c[i].write_bandwidth &&
c[i].read_latency && c[i].write_latency)
continue;
return false;
}
return true;
}
static void set_min_bandwidth(struct access_coordinate *c, unsigned int bw)
{
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
c[i].write_bandwidth = min(c[i].write_bandwidth, bw);
c[i].read_bandwidth = min(c[i].read_bandwidth, bw);
}
}
static void set_access_coordinates(struct access_coordinate *out,
struct access_coordinate *in)
{
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++)
Annotation
- Immediate include surface: `linux/platform_device.h`, `linux/memregion.h`, `linux/workqueue.h`, `linux/debugfs.h`, `linux/device.h`, `linux/module.h`, `linux/pci.h`, `linux/slab.h`.
- Detected declarations: `struct cxl_find_port_ctx`, `struct detach_ctx`, `function devices`, `function cxl_num_decoders_committed`, `function devtype_show`, `function cxl_device_id`, `function modalias_show`, `function start_show`, `function size_show`, `function target_type_show`.
- Atlas domain: Driver Families / drivers/cxl.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.