drivers/cxl/core/trace.h

Source file repositories/reference/linux-study-clean/drivers/cxl/core/trace.h

File Facts

System
Linux kernel
Corpus path
drivers/cxl/core/trace.h
Extension
.h
Size
42077 bytes
Lines
1114
Domain
Driver Families
Bucket
drivers/cxl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (cxlr) {
			__assign_str(region_name);
			uuid_copy(&__entry->region_uuid, &cxlr->params.uuid);
		} else {
			__assign_str(region_name);
			uuid_copy(&__entry->region_uuid, &uuid_null);
		}
		__entry->cme_threshold_ev_flags = rec->cme_threshold_ev_flags;
		if (rec->media_hdr.descriptor & CXL_GMER_EVT_DESC_THRESHOLD_EVENT)
			__entry->cme_count = get_unaligned_le24(rec->cme_count);
		else
			__entry->cme_count = 0;
	),

	CXL_EVT_TP_printk("dpa=%llx dpa_flags='%s' " \
		"descriptor='%s' type='%s' sub_type='%s' " \
		"transaction_type='%s' channel=%u rank=%u " \
		"device=%x validity_flags='%s' " \
		"comp_id=%s comp_id_pldm_valid_flags='%s' " \
		"pldm_entity_id=%s pldm_resource_id=%s " \
		"hpa=%llx hpa_alias0=%llx region=%s region_uuid=%pUb " \
		"cme_threshold_ev_flags='%s' cme_count=%u",
		__entry->dpa, show_dpa_flags(__entry->dpa_flags),
		show_event_desc_flags(__entry->descriptor),
		show_gmer_mem_event_type(__entry->type),
		show_mem_event_sub_type(__entry->sub_type),
		show_trans_type(__entry->transaction_type),
		__entry->channel, __entry->rank, __entry->device,
		show_valid_flags(__entry->validity_flags),
		__print_hex(__entry->comp_id, CXL_EVENT_GEN_MED_COMP_ID_SIZE),
		show_comp_id_pldm_flags(__entry->comp_id[0]),
		show_pldm_entity_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT,
				    CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
		show_pldm_resource_id(__entry->validity_flags, CXL_GMER_VALID_COMPONENT,
				      CXL_GMER_VALID_COMPONENT_ID_FORMAT, __entry->comp_id),
		__entry->hpa, __entry->hpa_alias0, __get_str(region_name), &__entry->region_uuid,
		show_cme_threshold_ev_flags(__entry->cme_threshold_ev_flags), __entry->cme_count
	)
);

/*
 * DRAM Event Record - DER
 *
 * CXL rev 3.1 section 8.2.9.2.1.2; Table 8-46
 */
/*
 * DRAM Event Record defines many fields the same as the General Media Event
 * Record.  Reuse those definitions as appropriate.
 */
#define CXL_DER_MEM_EVT_TYPE_ECC_ERROR			0x00
#define CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR	0x01
#define CXL_DER_MEM_EVT_TYPE_INV_ADDR			0x02
#define CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR		0x03
#define CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION	0x04
#define CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE	0x05
#define CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION		0x06
#define show_dram_mem_event_type(type)	__print_symbolic(type,					\
	{ CXL_DER_MEM_EVT_TYPE_ECC_ERROR,		"ECC Error" },				\
	{ CXL_DER_MEM_EVT_TYPE_SCRUB_MEDIA_ECC_ERROR,	"Scrub Media ECC Error" },		\
	{ CXL_DER_MEM_EVT_TYPE_INV_ADDR,		"Invalid Address" },			\
	{ CXL_DER_MEM_EVT_TYPE_DATA_PATH_ERROR,		"Data Path Error" },			\
	{ CXL_DER_MEM_EVT_TYPE_TE_STATE_VIOLATION,	"TE State Violation" },			\
	{ CXL_DER_MEM_EVT_TYPE_AP_CME_COUNTER_EXPIRE,	"Adv Prog CME Counter Expiration" },	\
	{ CXL_DER_MEM_EVT_TYPE_CKID_VIOLATION,		"CKID Violation" }			\
)

#define CXL_DER_VALID_CHANNEL				BIT(0)
#define CXL_DER_VALID_RANK				BIT(1)
#define CXL_DER_VALID_NIBBLE				BIT(2)
#define CXL_DER_VALID_BANK_GROUP			BIT(3)
#define CXL_DER_VALID_BANK				BIT(4)
#define CXL_DER_VALID_ROW				BIT(5)
#define CXL_DER_VALID_COLUMN				BIT(6)
#define CXL_DER_VALID_CORRECTION_MASK			BIT(7)
#define CXL_DER_VALID_COMPONENT				BIT(8)
#define CXL_DER_VALID_COMPONENT_ID_FORMAT		BIT(9)
#define CXL_DER_VALID_SUB_CHANNEL			BIT(10)
#define show_dram_valid_flags(flags)	__print_flags(flags, "|",			\
	{ CXL_DER_VALID_CHANNEL,			"CHANNEL"		},	\
	{ CXL_DER_VALID_RANK,				"RANK"			},	\
	{ CXL_DER_VALID_NIBBLE,				"NIBBLE"		},	\
	{ CXL_DER_VALID_BANK_GROUP,			"BANK GROUP"		},	\
	{ CXL_DER_VALID_BANK,				"BANK"			},	\
	{ CXL_DER_VALID_ROW,				"ROW"			},	\
	{ CXL_DER_VALID_COLUMN,				"COLUMN"		},	\
	{ CXL_DER_VALID_CORRECTION_MASK,		"CORRECTION MASK"	},	\
	{ CXL_DER_VALID_COMPONENT,			"COMPONENT"		},	\
	{ CXL_DER_VALID_COMPONENT_ID_FORMAT,		"COMPONENT PLDM FORMAT"	},	\
	{ CXL_DER_VALID_SUB_CHANNEL,			"SUB CHANNEL"		}	\
)

Annotation

Implementation Notes