drivers/dma/amd/qdma/qdma.c

Source file repositories/reference/linux-study-clean/drivers/dma/amd/qdma/qdma.c

File Facts

System
Linux kernel
Corpus path
drivers/dma/amd/qdma/qdma.c
Extension
.c
Size
28521 bytes
Lines
1144
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (ret) {
			qdma_err(qdev, "Failed to clear ctxt %d", type[i]);
			return ret;
		}
	}

	return 0;
}

static int qdma_setup_fmap_context(struct qdma_device *qdev)
{
	u32 ctxt[QDMA_CTXT_REGMAP_LEN];
	struct qdma_ctxt_fmap fmap;
	int ret;

	ret = qdma_prog_context(qdev, QDMA_CTXT_FMAP, QDMA_CTXT_CLEAR,
				qdev->fid, NULL);
	if (ret) {
		qdma_err(qdev, "Failed clearing context");
		return ret;
	}

	fmap.qbase = 0;
	fmap.qmax = qdev->chan_num * 2;
	qdma_prep_fmap_context(qdev, &fmap, ctxt);
	ret = qdma_prog_context(qdev, QDMA_CTXT_FMAP, QDMA_CTXT_WRITE,
				qdev->fid, ctxt);
	if (ret)
		qdma_err(qdev, "Failed setup fmap, ret %d", ret);

	return ret;
}

static int qdma_setup_queue_context(struct qdma_device *qdev,
				    const struct qdma_ctxt_sw_desc *sw_desc,
				    enum dma_transfer_direction dir, u16 qid)
{
	u32 ctxt[QDMA_CTXT_REGMAP_LEN];
	enum qdma_ctxt_type type;
	int ret;

	if (dir == DMA_MEM_TO_DEV)
		type = QDMA_CTXT_DESC_SW_H2C;
	else
		type = QDMA_CTXT_DESC_SW_C2H;

	qdma_prep_sw_desc_context(qdev, sw_desc, ctxt);
	/* Setup SW descriptor context */
	ret = qdma_prog_context(qdev, type, QDMA_CTXT_WRITE, qid, ctxt);
	if (ret)
		qdma_err(qdev, "Failed setup SW desc ctxt for queue: %d", qid);

	return ret;
}

/*
 * Enable or disable memory-mapped DMA engines
 * 1: enable, 0: disable
 */
static int qdma_sgdma_control(struct qdma_device *qdev, u32 ctrl)
{
	int ret;

	ret = qdma_reg_write(qdev, &ctrl, QDMA_REGO_MM_H2C_CTRL);
	ret |= qdma_reg_write(qdev, &ctrl, QDMA_REGO_MM_C2H_CTRL);

	return ret;
}

static int qdma_get_hw_info(struct qdma_device *qdev)
{
	struct qdma_platdata *pdata = dev_get_platdata(&qdev->pdev->dev);
	u32 value = 0;
	int ret;

	ret = qdma_reg_read(qdev, &value, QDMA_REGO_QUEUE_COUNT);
	if (ret)
		return ret;

	value = qdma_get_field(qdev, &value, QDMA_REGF_QUEUE_COUNT) + 1;
	if (pdata->max_mm_channels * 2 > value) {
		qdma_err(qdev, "not enough hw queues %d", value);
		return -EINVAL;
	}
	qdev->chan_num = pdata->max_mm_channels;

	ret = qdma_reg_read(qdev, &qdev->fid, QDMA_REGO_FUNC_ID);
	if (ret)
		return ret;

Annotation

Implementation Notes