drivers/dma/dw/idma32.c

Source file repositories/reference/linux-study-clean/drivers/dma/dw/idma32.c

File Facts

System
Linux kernel
Corpus path
drivers/dma/dw/idma32.c
Extension
.c
Size
7619 bytes
Lines
295
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
// Copyright (C) 2013,2018,2020-2021 Intel Corporation

#include <linux/bitops.h>
#include <linux/dmaengine.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/types.h>

#include "internal.h"

#define DMA_CTL_CH(x)			(0x1000 + (x) * 4)
#define DMA_SRC_ADDR_FILLIN(x)		(0x1100 + (x) * 4)
#define DMA_DST_ADDR_FILLIN(x)		(0x1200 + (x) * 4)
#define DMA_XBAR_SEL(x)			(0x1300 + (x) * 4)
#define DMA_REGACCESS_CHID_CFG		(0x1400)

#define CTL_CH_TRANSFER_MODE_MASK	GENMASK(1, 0)
#define CTL_CH_TRANSFER_MODE_S2S	0
#define CTL_CH_TRANSFER_MODE_S2D	1
#define CTL_CH_TRANSFER_MODE_D2S	2
#define CTL_CH_TRANSFER_MODE_D2D	3
#define CTL_CH_RD_RS_MASK		GENMASK(4, 3)
#define CTL_CH_WR_RS_MASK		GENMASK(6, 5)
#define CTL_CH_RD_NON_SNOOP_BIT		BIT(8)
#define CTL_CH_WR_NON_SNOOP_BIT		BIT(9)

#define XBAR_SEL_DEVID_MASK		GENMASK(15, 0)
#define XBAR_SEL_RX_TX_BIT		BIT(16)
#define XBAR_SEL_RX_TX_SHIFT		16

#define REGACCESS_CHID_MASK		GENMASK(2, 0)

static unsigned int idma32_get_slave_devfn(struct dw_dma_chan *dwc)
{
	struct device *slave = dwc->chan.slave;

	if (!slave || !dev_is_pci(slave))
		return 0;

	return to_pci_dev(slave)->devfn;
}

static void idma32_initialize_chan_xbar(struct dw_dma_chan *dwc)
{
	struct dw_dma *dw = to_dw_dma(dwc->chan.device);
	void __iomem *misc = __dw_regs(dw);
	u32 cfghi = 0, cfglo = 0;
	u8 dst_id, src_id;
	u32 value;

	/* DMA Channel ID Configuration register must be programmed first */
	value = readl(misc + DMA_REGACCESS_CHID_CFG);

	value &= ~REGACCESS_CHID_MASK;
	value |= dwc->chan.chan_id;

	writel(value, misc + DMA_REGACCESS_CHID_CFG);

	/* Configure channel attributes */
	value = readl(misc + DMA_CTL_CH(dwc->chan.chan_id));

	value &= ~(CTL_CH_RD_NON_SNOOP_BIT | CTL_CH_WR_NON_SNOOP_BIT);
	value &= ~(CTL_CH_RD_RS_MASK | CTL_CH_WR_RS_MASK);
	value &= ~CTL_CH_TRANSFER_MODE_MASK;

	switch (dwc->direction) {
	case DMA_MEM_TO_DEV:
		value |= CTL_CH_TRANSFER_MODE_D2S;
		value |= CTL_CH_WR_NON_SNOOP_BIT;
		break;
	case DMA_DEV_TO_MEM:
		value |= CTL_CH_TRANSFER_MODE_S2D;
		value |= CTL_CH_RD_NON_SNOOP_BIT;
		break;
	default:
		/*
		 * Memory-to-Memory and Device-to-Device are ignored for now.
		 *
		 * For Memory-to-Memory transfers we would need to set mode
		 * and disable snooping on both sides.
		 */
		return;
	}

	writel(value, misc + DMA_CTL_CH(dwc->chan.chan_id));

	/* Configure crossbar selection */

Annotation

Implementation Notes