drivers/dma/img-mdc-dma.c
Source file repositories/reference/linux-study-clean/drivers/dma/img-mdc-dma.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/dma/img-mdc-dma.c- Extension
.c- Size
- 28334 bytes
- Lines
- 1086
- Domain
- Driver Families
- Bucket
- drivers/dma
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/dma-mapping.hlinux/dmaengine.hlinux/dmapool.hlinux/interrupt.hlinux/io.hlinux/irq.hlinux/kernel.hlinux/mfd/syscon.hlinux/module.hlinux/of.hlinux/of_dma.hlinux/platform_device.hlinux/pm_runtime.hlinux/regmap.hlinux/slab.hlinux/spinlock.hdmaengine.hvirt-dma.h
Detected Declarations
struct mdc_hw_list_descstruct mdc_tx_descstruct mdc_chanstruct mdc_dma_soc_datastruct mdc_dmafunction mdc_readlfunction mdc_writelfunction mdc_chan_readlfunction mdc_chan_writelfunction to_mdc_widthfunction mdc_set_read_widthfunction mdc_set_write_widthfunction mdc_list_desc_configfunction mdc_list_desc_freefunction mdc_desc_freefunction mdc_check_slave_widthfunction for_each_sgfunction mdc_issue_descfunction mdc_issue_pendingfunction mdc_tx_statusfunction mdc_get_new_eventsfunction mdc_terminate_allfunction mdc_synchronizefunction mdc_slave_configfunction mdc_alloc_chan_resourcesfunction mdc_free_chan_resourcesfunction mdc_chan_irqfunction list_for_each_entryfunction pistachio_mdc_enable_chanfunction pistachio_mdc_disable_chanfunction img_mdc_runtime_suspendfunction img_mdc_runtime_resumefunction mdc_dma_probefunction mdc_dma_removefunction list_for_each_entry_safefunction img_mdc_suspend_latefunction img_mdc_resume_early
Annotated Snippet
struct mdc_hw_list_desc {
u32 gen_conf;
u32 readport_conf;
u32 read_addr;
u32 write_addr;
u32 xfer_size;
u32 node_addr;
u32 cmds_done;
u32 ctrl_status;
/*
* Not part of the list descriptor, but instead used by the CPU to
* traverse the list.
*/
struct mdc_hw_list_desc *next_desc;
};
struct mdc_tx_desc {
struct mdc_chan *chan;
struct virt_dma_desc vd;
dma_addr_t list_phys;
struct mdc_hw_list_desc *list;
bool cyclic;
bool cmd_loaded;
unsigned int list_len;
unsigned int list_period_len;
size_t list_xfer_size;
unsigned int list_cmds_done;
};
struct mdc_chan {
struct mdc_dma *mdma;
struct virt_dma_chan vc;
struct dma_slave_config config;
struct mdc_tx_desc *desc;
int irq;
unsigned int periph;
unsigned int thread;
unsigned int chan_nr;
};
struct mdc_dma_soc_data {
void (*enable_chan)(struct mdc_chan *mchan);
void (*disable_chan)(struct mdc_chan *mchan);
};
struct mdc_dma {
struct dma_device dma_dev;
void __iomem *regs;
struct clk *clk;
struct dma_pool *desc_pool;
struct regmap *periph_regs;
spinlock_t lock;
unsigned int nr_threads;
unsigned int nr_channels;
unsigned int bus_width;
unsigned int max_burst_mult;
unsigned int max_xfer_size;
const struct mdc_dma_soc_data *soc;
struct mdc_chan channels[MDC_MAX_DMA_CHANNELS];
};
static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg)
{
return readl(mdma->regs + reg);
}
static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg)
{
writel(val, mdma->regs + reg);
}
static inline u32 mdc_chan_readl(struct mdc_chan *mchan, u32 reg)
{
return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg);
}
static inline void mdc_chan_writel(struct mdc_chan *mchan, u32 val, u32 reg)
{
mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg);
}
static inline struct mdc_chan *to_mdc_chan(struct dma_chan *c)
{
return container_of(to_virt_chan(c), struct mdc_chan, vc);
}
static inline struct mdc_tx_desc *to_mdc_desc(struct dma_async_tx_descriptor *t)
{
struct virt_dma_desc *vdesc = container_of(t, struct virt_dma_desc, tx);
Annotation
- Immediate include surface: `linux/clk.h`, `linux/dma-mapping.h`, `linux/dmaengine.h`, `linux/dmapool.h`, `linux/interrupt.h`, `linux/io.h`, `linux/irq.h`, `linux/kernel.h`.
- Detected declarations: `struct mdc_hw_list_desc`, `struct mdc_tx_desc`, `struct mdc_chan`, `struct mdc_dma_soc_data`, `struct mdc_dma`, `function mdc_readl`, `function mdc_writel`, `function mdc_chan_readl`, `function mdc_chan_writel`, `function to_mdc_width`.
- Atlas domain: Driver Families / drivers/dma.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.