drivers/dma/imx-sdma.c

Source file repositories/reference/linux-study-clean/drivers/dma/imx-sdma.c

File Facts

System
Linux kernel
Corpus path
drivers/dma/imx-sdma.c
Extension
.c
Size
66436 bytes
Lines
2431
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sdma_script_start_addrs {
	s32 ap_2_ap_addr;
	s32 ap_2_bp_addr;
	s32 ap_2_ap_fixed_addr;
	s32 bp_2_ap_addr;
	s32 loopback_on_dsp_side_addr;
	s32 mcu_interrupt_only_addr;
	s32 firi_2_per_addr;
	s32 firi_2_mcu_addr;
	s32 per_2_firi_addr;
	s32 mcu_2_firi_addr;
	s32 uart_2_per_addr;
	s32 uart_2_mcu_addr;
	s32 per_2_app_addr;
	s32 mcu_2_app_addr;
	s32 per_2_per_addr;
	s32 uartsh_2_per_addr;
	s32 uartsh_2_mcu_addr;
	s32 per_2_shp_addr;
	s32 mcu_2_shp_addr;
	s32 ata_2_mcu_addr;
	s32 mcu_2_ata_addr;
	s32 app_2_per_addr;
	s32 app_2_mcu_addr;
	s32 shp_2_per_addr;
	s32 shp_2_mcu_addr;
	s32 mshc_2_mcu_addr;
	s32 mcu_2_mshc_addr;
	s32 spdif_2_mcu_addr;
	s32 mcu_2_spdif_addr;
	s32 asrc_2_mcu_addr;
	s32 ext_mem_2_ipu_addr;
	s32 descrambler_addr;
	s32 dptc_dvfs_addr;
	s32 utra_addr;
	s32 ram_code_start_addr;
	/* End of v1 array */
	union {	s32 v1_end; s32 mcu_2_ssish_addr; };
	s32 ssish_2_mcu_addr;
	s32 hdmi_dma_addr;
	/* End of v2 array */
	union { s32 v2_end; s32 zcanfd_2_mcu_addr; };
	s32 zqspi_2_mcu_addr;
	s32 mcu_2_ecspi_addr;
	s32 mcu_2_sai_addr;
	s32 sai_2_mcu_addr;
	s32 uart_2_mcu_rom_addr;
	s32 uartsh_2_mcu_rom_addr;
	s32 i2c_2_mcu_addr;
	s32 mcu_2_i2c_addr;
	/* End of v3 array */
	union { s32 v3_end; s32 mcu_2_zqspi_addr; };
	/* End of v4 array */
	s32 v4_end[];
};

/*
 * Mode/Count of data node descriptors - IPCv2
 */
struct sdma_mode_count {
#define SDMA_BD_MAX_CNT	0xffff
	u32 count   : 16; /* size of the buffer pointed by this BD */
	u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
	u32 command :  8; /* command mostly used for channel 0 */
};

/*
 * Buffer descriptor
 */
struct sdma_buffer_descriptor {
	struct sdma_mode_count  mode;
	u32 buffer_addr;	/* address of the buffer described */
	u32 ext_buffer_addr;	/* extended buffer address */
} __attribute__ ((packed));

/**
 * struct sdma_channel_control - Channel control Block
 *
 * @current_bd_ptr:	current buffer descriptor processed
 * @base_bd_ptr:	first element of buffer descriptor array
 * @unused:		padding. The SDMA engine expects an array of 128 byte
 *			control blocks
 */
struct sdma_channel_control {
	u32 current_bd_ptr;
	u32 base_bd_ptr;
	u32 unused[2];
} __attribute__ ((packed));

/**

Annotation

Implementation Notes