drivers/dma/ioat/registers.h

Source file repositories/reference/linux-study-clean/drivers/dma/ioat/registers.h

File Facts

System
Linux kernel
Corpus path
drivers/dma/ioat/registers.h
Extension
.h
Size
9675 bytes
Lines
252
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _IOAT_REGISTERS_H_
#define _IOAT_REGISTERS_H_

#define IOAT_PCI_DMACTRL_OFFSET			0x48
#define IOAT_PCI_DMACTRL_DMA_EN			0x00000001
#define IOAT_PCI_DMACTRL_MSI_EN			0x00000002

#define IOAT_PCI_DEVICE_ID_OFFSET		0x02
#define IOAT_PCI_DMAUNCERRSTS_OFFSET		0x148
#define IOAT_PCI_CHANERR_INT_OFFSET		0x180
#define IOAT_PCI_CHANERRMASK_INT_OFFSET		0x184

/* MMIO Device Registers */
#define IOAT_CHANCNT_OFFSET			0x00	/*  8-bit */

#define IOAT_XFERCAP_OFFSET			0x01	/*  8-bit */
#define IOAT_XFERCAP_4KB			12
#define IOAT_XFERCAP_8KB			13
#define IOAT_XFERCAP_16KB			14
#define IOAT_XFERCAP_32KB			15
#define IOAT_XFERCAP_32GB			0

#define IOAT_GENCTRL_OFFSET			0x02	/*  8-bit */
#define IOAT_GENCTRL_DEBUG_EN			0x01

#define IOAT_INTRCTRL_OFFSET			0x03	/*  8-bit */
#define IOAT_INTRCTRL_MASTER_INT_EN		0x01	/* Master Interrupt Enable */
#define IOAT_INTRCTRL_INT_STATUS		0x02	/* ATTNSTATUS -or- Channel Int */
#define IOAT_INTRCTRL_INT			0x04	/* INT_STATUS -and- MASTER_INT_EN */
#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL	0x08	/* Enable all MSI-X vectors */

#define IOAT_ATTNSTATUS_OFFSET			0x04	/* Each bit is a channel */

#define IOAT_VER_OFFSET				0x08	/*  8-bit */
#define IOAT_VER_MAJOR_MASK			0xF0
#define IOAT_VER_MINOR_MASK			0x0F
#define GET_IOAT_VER_MAJOR(x)			(((x) & IOAT_VER_MAJOR_MASK) >> 4)
#define GET_IOAT_VER_MINOR(x)			((x) & IOAT_VER_MINOR_MASK)

#define IOAT_PERPORTOFFSET_OFFSET		0x0A	/* 16-bit */

#define IOAT_INTRDELAY_OFFSET			0x0C	/* 16-bit */
#define IOAT_INTRDELAY_MASK			0x3FFF	/* Interrupt Delay Time */
#define IOAT_INTRDELAY_COALESE_SUPPORT		0x8000	/* Interrupt Coalescing Supported */

#define IOAT_DEVICE_STATUS_OFFSET		0x0E	/* 16-bit */
#define IOAT_DEVICE_STATUS_DEGRADED_MODE	0x0001
#define IOAT_DEVICE_MMIO_RESTRICTED		0x0002
#define IOAT_DEVICE_MEMORY_BYPASS		0x0004
#define IOAT_DEVICE_ADDRESS_REMAPPING		0x0008

#define IOAT_DMA_CAP_OFFSET			0x10	/* 32-bit */
#define IOAT_CAP_PAGE_BREAK			0x00000001
#define IOAT_CAP_CRC				0x00000002
#define IOAT_CAP_SKIP_MARKER			0x00000004
#define IOAT_CAP_DCA				0x00000010
#define IOAT_CAP_CRC_MOVE			0x00000020
#define IOAT_CAP_FILL_BLOCK			0x00000040
#define IOAT_CAP_APIC				0x00000080
#define IOAT_CAP_XOR				0x00000100
#define IOAT_CAP_PQ				0x00000200
#define IOAT_CAP_DWBES				0x00002000
#define IOAT_CAP_RAID16SS			0x00020000
#define IOAT_CAP_DPS				0x00800000

#define IOAT_PREFETCH_LIMIT_OFFSET		0x4C	/* CHWPREFLMT */

#define IOAT_CHANNEL_MMIO_SIZE			0x80	/* Each Channel MMIO space is this size */

/* DMA Channel Registers */
#define IOAT_CHANCTRL_OFFSET			0x00	/* 16-bit Channel Control Register */
#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK	0xF000
#define IOAT3_CHANCTRL_COMPL_DCA_EN		0x0200
#define IOAT_CHANCTRL_CHANNEL_IN_USE		0x0100
#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL	0x0020
#define IOAT_CHANCTRL_ERR_INT_EN		0x0010
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN		0x0008
#define IOAT_CHANCTRL_ERR_COMPLETION_EN		0x0004
#define IOAT_CHANCTRL_INT_REARM			0x0001
#define IOAT_CHANCTRL_RUN			(IOAT_CHANCTRL_INT_REARM |\
						 IOAT_CHANCTRL_ERR_INT_EN |\
						 IOAT_CHANCTRL_ERR_COMPLETION_EN |\
						 IOAT_CHANCTRL_ANY_ERR_ABORT_EN)

#define IOAT_DMA_COMP_OFFSET			0x02	/* 16-bit DMA channel compatibility */
#define IOAT_DMA_COMP_V1			0x0001	/* Compatibility with DMA version 1 */
#define IOAT_DMA_COMP_V2			0x0002	/* Compatibility with DMA version 2 */

#define IOAT_CHANSTS_OFFSET		0x08	/* 64-bit Channel Status Register */
#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR	(~0x3fULL)

Annotation

Implementation Notes