drivers/dma/mmp_pdma.c

Source file repositories/reference/linux-study-clean/drivers/dma/mmp_pdma.c

File Facts

System
Linux kernel
Corpus path
drivers/dma/mmp_pdma.c
Extension
.c
Size
36897 bytes
Lines
1369
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mmp_pdma_desc_hw {
	u32 ddadr;	/* Points to the next descriptor + flags */
	u32 dsadr;	/* DSADR value for the current transfer */
	u32 dtadr;	/* DTADR value for the current transfer */
	u32 dcmd;	/* DCMD value for the current transfer */
	/*
	 * The following 32-bit words are only used in the 64-bit, ie.
	 * LPAE (Long Physical Address Extension) mode.
	 * They are used to specify the high 32 bits of the descriptor's
	 * addresses.
	 */
	u32 ddadrh;	/* High 32-bit of DDADR */
	u32 dsadrh;	/* High 32-bit of DSADR */
	u32 dtadrh;	/* High 32-bit of DTADR */
	u32 rsvd;	/* reserved */
} __aligned(32);

struct mmp_pdma_desc_sw {
	struct mmp_pdma_desc_hw desc;
	struct list_head node;
	struct list_head tx_list;
	struct dma_async_tx_descriptor async_tx;
};

struct mmp_pdma_phy;

struct mmp_pdma_chan {
	struct device *dev;
	struct dma_chan chan;
	struct dma_async_tx_descriptor desc;
	struct mmp_pdma_phy *phy;
	enum dma_transfer_direction dir;
	struct dma_slave_config slave_config;

	struct mmp_pdma_desc_sw *cyclic_first;	/* first desc_sw if channel
						 * is in cyclic mode */

	/* channel's basic info */
	struct tasklet_struct tasklet;
	u32 dcmd;
	u32 drcmr;
	u32 dev_addr;

	/* list for desc */
	spinlock_t desc_lock;		/* Descriptor list lock */
	struct list_head chain_pending;	/* Link descriptors queue for pending */
	struct list_head chain_running;	/* Link descriptors queue for running */
	bool idle;			/* channel statue machine */
	bool byte_align;

	struct dma_pool *desc_pool;	/* Descriptors pool */
};

struct mmp_pdma_phy {
	int idx;
	void __iomem *base;
	struct mmp_pdma_chan *vchan;
};

/**
 * struct mmp_pdma_ops - Operations for the MMP PDMA controller
 *
 * Hardware Register Operations (read/write hardware registers):
 * @write_next_addr: Function to program address of next descriptor into
 *                   DDADR/DDADRH
 * @read_src_addr: Function to read the source address from DSADR/DSADRH
 * @read_dst_addr: Function to read the destination address from DTADR/DTADRH
 *
 * Descriptor Memory Operations (manipulate descriptor structs in memory):
 * @set_desc_next_addr: Function to set next descriptor address in descriptor
 * @set_desc_src_addr: Function to set the source address in descriptor
 * @set_desc_dst_addr: Function to set the destination address in descriptor
 * @get_desc_src_addr: Function to get the source address from descriptor
 * @get_desc_dst_addr: Function to get the destination address from descriptor
 *
 * Controller Configuration:
 * @run_bits:   Control bits in DCSR register for channel start/stop
 * @dma_width:  DMA addressing width in bits (32 or 64). Determines the
 *              DMA mask capability of the controller hardware.
 */
struct mmp_pdma_ops {
	/* Hardware Register Operations */
	void (*write_next_addr)(struct mmp_pdma_phy *phy, dma_addr_t addr);
	u64 (*read_src_addr)(struct mmp_pdma_phy *phy);
	u64 (*read_dst_addr)(struct mmp_pdma_phy *phy);

	/* Descriptor Memory Operations */
	void (*set_desc_next_addr)(struct mmp_pdma_desc_hw *desc,
				   dma_addr_t addr);
	void (*set_desc_src_addr)(struct mmp_pdma_desc_hw *desc,

Annotation

Implementation Notes