drivers/dma/ppc4xx/adma.c
Source file repositories/reference/linux-study-clean/drivers/dma/ppc4xx/adma.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/dma/ppc4xx/adma.c- Extension
.c- Size
- 126855 bytes
- Lines
- 4626
- Domain
- Driver Families
- Bucket
- drivers/dma
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/module.hlinux/async_tx.hlinux/delay.hlinux/dma-mapping.hlinux/spinlock.hlinux/interrupt.hlinux/slab.hlinux/uaccess.hlinux/proc_fs.hlinux/of.hlinux/of_address.hlinux/of_irq.hlinux/platform_device.hasm/dcr.hasm/dcr-regs.hadma.h../dmaengine.h
Detected Declarations
struct ppc_dma_chan_refenum ppc_adma_init_codefunction print_cbfunction print_cb_listfunction prep_dma_xor_dbgfunction prep_dma_pq_dbgfunction prep_dma_pqzero_sum_dbgfunction Commandfunction ppc440spe_desc_init_null_xorfunction ppc440spe_desc_init_xorfunction ppc440spe_desc_init_dma2pqfunction ppc440spe_desc_init_dma01pqfunction list_for_each_entryfunction list_for_each_entry_fromfunction list_for_each_entry_fromfunction ppc440spe_desc_init_dma01pqzero_sumfunction ppc440spe_desc_init_memcpyfunction ppc440spe_desc_set_src_addrfunction ppc440spe_desc_set_src_multfunction ppc440spe_desc_set_dest_addrfunction ppc440spe_desc_set_byte_countfunction ppc440spe_desc_set_rxor_block_sizefunction ppc440spe_desc_set_dcheckfunction ppc440spe_xor_set_linkfunction ppc440spe_desc_set_linkfunction ppc440spe_desc_get_linkfunction ppc440spe_desc_is_alignedfunction ppc440spe_chan_xor_slot_countfunction ppc440spe_dma2_pq_slot_countfunction ppc440spe_adma_device_clear_eot_statusfunction list_for_each_entryfunction ppc440spe_chan_is_busyfunction ppc440spe_chan_set_first_xor_descriptorfunction ppc440spe_dma_put_descfunction ppc440spe_chan_appendfunction list_for_each_entry_continuefunction ppc440spe_chan_get_current_descriptorfunction ppc440spe_chan_runfunction ppc440spe_can_rxorfunction ppc440spe_adma_estimatefunction ppc440spe_async_tx_find_best_channelfunction list_for_each_entryfunction ppc440spe_get_group_entryfunction list_for_each_entryfunction ppc440spe_adma_free_slotsfunction ppc440spe_adma_run_tx_complete_actionsfunction ppc440spe_adma_clean_slotfunction callbacks
Annotated Snippet
static ssize_t devices_show(struct device_driver *dev, char *buf)
{
ssize_t size = 0;
int i;
for (i = 0; i < PPC440SPE_ADMA_ENGINES_NUM; i++) {
if (ppc440spe_adma_devices[i] == -1)
continue;
size += sysfs_emit_at(buf, size, "PPC440SP(E)-ADMA.%d: %s\n",
i, ppc_adma_errors[ppc440spe_adma_devices[i]]);
}
return size;
}
static DRIVER_ATTR_RO(devices);
static ssize_t enable_show(struct device_driver *dev, char *buf)
{
return sysfs_emit(buf, "PPC440SP(e) RAID-6 capabilities are %sABLED.\n",
ppc440spe_r6_enabled ? "EN" : "DIS");
}
static ssize_t enable_store(struct device_driver *dev, const char *buf,
size_t count)
{
unsigned long val;
int err;
if (!count || count > 11)
return -EINVAL;
if (!ppc440spe_r6_tchan)
return -EFAULT;
/* Write a key */
err = kstrtoul(buf, 16, &val);
if (err)
return err;
dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_XORBA, val);
isync();
/* Verify whether it really works now */
if (ppc440spe_test_raid6(ppc440spe_r6_tchan) == 0) {
pr_info("PPC440SP(e) RAID-6 has been activated "
"successfully\n");
ppc440spe_r6_enabled = 1;
} else {
pr_info("PPC440SP(e) RAID-6 hasn't been activated!"
" Error key ?\n");
ppc440spe_r6_enabled = 0;
}
return count;
}
static DRIVER_ATTR_RW(enable);
static ssize_t poly_show(struct device_driver *dev, char *buf)
{
ssize_t size = 0;
u32 reg;
#ifdef CONFIG_440SP
/* 440SP has fixed polynomial */
reg = 0x4d;
#else
reg = dcr_read(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL);
reg >>= MQ0_CFBHL_POLY;
reg &= 0xFF;
#endif
size = sysfs_emit(buf, "PPC440SP(e) RAID-6 driver "
"uses 0x1%02x polynomial.\n", reg);
return size;
}
static ssize_t poly_store(struct device_driver *dev, const char *buf,
size_t count)
{
unsigned long reg, val;
int err;
#ifdef CONFIG_440SP
/* 440SP uses default 0x14D polynomial only */
return -EINVAL;
#endif
if (!count || count > 6)
return -EINVAL;
/* e.g., 0x14D or 0x11D */
err = kstrtoul(buf, 16, &val);
if (err)
Annotation
- Immediate include surface: `linux/init.h`, `linux/module.h`, `linux/async_tx.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/spinlock.h`, `linux/interrupt.h`, `linux/slab.h`.
- Detected declarations: `struct ppc_dma_chan_ref`, `enum ppc_adma_init_code`, `function print_cb`, `function print_cb_list`, `function prep_dma_xor_dbg`, `function prep_dma_pq_dbg`, `function prep_dma_pqzero_sum_dbg`, `function Command`, `function ppc440spe_desc_init_null_xor`, `function ppc440spe_desc_init_xor`.
- Atlas domain: Driver Families / drivers/dma.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.