drivers/dma/qcom/hidma_mgmt.h

File Facts

System

Linux kernel

Corpus path

drivers/dma/qcom/hidma_mgmt.h

Extension

.h

Size

688 bytes

Lines

32

Domain

Driver Families

Bucket

drivers/dma

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct hidma_mgmt_dev

Annotated Snippet

struct hidma_mgmt_dev {
	u8 hw_version_major;
	u8 hw_version_minor;

	u32 max_wr_xactions;
	u32 max_rd_xactions;
	u32 max_write_request;
	u32 max_read_request;
	u32 dma_channels;
	u32 chreset_timeout_cycles;
	u32 hw_version;
	u32 *priority;
	u32 *weight;

	/* Hardware device constants */
	void __iomem *virtaddr;
	resource_size_t addrsize;

	struct kobject **chroots;
	struct platform_device *pdev;
};

int hidma_mgmt_init_sys(struct hidma_mgmt_dev *dev);
int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev);

Annotation

• Detected declarations: `struct hidma_mgmt_dev`.
• Atlas domain: Driver Families / drivers/dma.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.