drivers/dma/sh/rz-dmac.c
Source file repositories/reference/linux-study-clean/drivers/dma/sh/rz-dmac.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/dma/sh/rz-dmac.c- Extension
.c- Size
- 33753 bytes
- Lines
- 1288
- Domain
- Driver Families
- Bucket
- drivers/dma
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/cleanup.hlinux/dma-mapping.hlinux/dmaengine.hlinux/interrupt.hlinux/iopoll.hlinux/irqchip/irq-renesas-rzv2h.hlinux/irqchip/irq-renesas-rzt2h.hlinux/list.hlinux/module.hlinux/of.hlinux/of_dma.hlinux/of_platform.hlinux/platform_device.hlinux/pm_runtime.hlinux/reset.hlinux/slab.hlinux/spinlock.h../dmaengine.h../virt-dma.h
Detected Declarations
struct rz_lmdescstruct rz_dmac_descstruct rz_dmac_chanstruct rz_dmac_icustruct rz_dmac_infostruct rz_dmacenum rz_dmac_prep_typefunction rz_dmac_writelfunction rz_dmac_ext_writelfunction rz_dmac_ext_readlfunction rz_dmac_ch_writelfunction rz_dmac_ch_readlfunction rz_lmdesc_setupfunction rz_dmac_lmdesc_recyclefunction rz_dmac_enable_hwfunction rz_dmac_disable_hwfunction rz_dmac_set_dmars_registerfunction rz_dmac_set_dma_req_nofunction rz_dmac_prepare_desc_for_memcpyfunction rz_dmac_prepare_descs_for_slave_sgfunction rz_dmac_xfer_descfunction rz_dmac_alloc_chan_resourcesfunction rz_dmac_free_chan_resourcesfunction list_for_each_entry_safefunction rz_dmac_prep_dma_memcpyfunction scoped_guardfunction rz_dmac_prep_slave_sgfunction scoped_guardfunction rz_dmac_terminate_allfunction rz_dmac_issue_pendingfunction rz_dmac_ds_to_val_mappingfunction rz_dmac_configfunction rz_dmac_virt_desc_freefunction rz_dmac_get_next_lmdescfunction rz_dmac_calculate_residue_bytes_in_vdfunction rz_dmac_chan_get_residuefunction rz_dmac_irq_handler_threadfunction list_for_each_entryfunction list_for_each_entryfunction rz_dmac_tx_statusfunction scoped_guardfunction rz_dmac_device_pausefunction rz_dmac_device_resumefunction rz_dmac_irq_handle_channelfunction rz_dmac_irq_handlerfunction rz_dmac_irq_handler_threadfunction rz_dmac_chan_filterfunction rz_dmac_chan_probe
Annotated Snippet
struct rz_lmdesc {
u32 header;
u32 sa;
u32 da;
u32 tb;
u32 chcfg;
u32 chitvl;
u32 chext;
u32 nxla;
};
struct rz_dmac_desc {
struct virt_dma_desc vd;
dma_addr_t src;
dma_addr_t dest;
size_t len;
struct list_head node;
enum dma_transfer_direction direction;
enum rz_dmac_prep_type type;
/* For slave sg */
struct scatterlist *sg;
unsigned int sgcount;
};
#define to_rz_dmac_desc(d) container_of(d, struct rz_dmac_desc, vd)
struct rz_dmac_chan {
struct virt_dma_chan vc;
void __iomem *ch_base;
void __iomem *ch_cmn_base;
unsigned int index;
struct rz_dmac_desc *desc;
int descs_allocated;
dma_addr_t src_per_address;
dma_addr_t dst_per_address;
u32 chcfg;
u32 chctrl;
int mid_rid;
struct list_head ld_free;
struct list_head ld_queue;
struct list_head ld_active;
struct {
struct rz_lmdesc *base;
struct rz_lmdesc *head;
struct rz_lmdesc *tail;
dma_addr_t base_dma;
} lmdesc;
};
#define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan)
struct rz_dmac_icu {
struct platform_device *pdev;
u8 dmac_index;
};
struct rz_dmac_info {
void (*icu_register_dma_req)(struct platform_device *icu_dev,
u8 dmac_index, u8 dmac_channel, u16 req_no);
u16 default_dma_req_no;
};
struct rz_dmac {
struct dma_device engine;
struct rz_dmac_icu icu;
const struct rz_dmac_info *info;
struct device *dev;
struct reset_control *rstc;
void __iomem *base;
void __iomem *ext_base;
unsigned int n_channels;
struct rz_dmac_chan *channels;
DECLARE_BITMAP(modules, 1024);
};
#define to_rz_dmac(d) container_of(d, struct rz_dmac, engine)
/*
* -----------------------------------------------------------------------------
* Registers
*/
#define CRTB 0x0020
#define CHSTAT 0x0024
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/cleanup.h`, `linux/dma-mapping.h`, `linux/dmaengine.h`, `linux/interrupt.h`, `linux/iopoll.h`, `linux/irqchip/irq-renesas-rzv2h.h`, `linux/irqchip/irq-renesas-rzt2h.h`.
- Detected declarations: `struct rz_lmdesc`, `struct rz_dmac_desc`, `struct rz_dmac_chan`, `struct rz_dmac_icu`, `struct rz_dmac_info`, `struct rz_dmac`, `enum rz_dmac_prep_type`, `function rz_dmac_writel`, `function rz_dmac_ext_writel`, `function rz_dmac_ext_readl`.
- Atlas domain: Driver Families / drivers/dma.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.