drivers/dma/txx9dmac.h

Source file repositories/reference/linux-study-clean/drivers/dma/txx9dmac.h

File Facts

System
Linux kernel
Corpus path
drivers/dma/txx9dmac.h
Extension
.h
Size
7750 bytes
Lines
305
Domain
Driver Families
Bucket
drivers/dma
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct txx9dmac_cregs {
#if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
	TXX9_DMA_REG32(CHAR);	/* Chain Address Register */
#else
	u64 CHAR;		/* Chain Address Register */
#endif
	u64 SAR;		/* Source Address Register */
	u64 DAR;		/* Destination Address Register */
	TXX9_DMA_REG32(CNTR);	/* Count Register */
	TXX9_DMA_REG32(SAIR);	/* Source Address Increment Register */
	TXX9_DMA_REG32(DAIR);	/* Destination Address Increment Register */
	TXX9_DMA_REG32(CCR);	/* Channel Control Register */
	TXX9_DMA_REG32(CSR);	/* Channel Status Register */
};
struct txx9dmac_cregs32 {
	u32 CHAR;
	u32 SAR;
	u32 DAR;
	u32 CNTR;
	u32 SAIR;
	u32 DAIR;
	u32 CCR;
	u32 CSR;
};

struct txx9dmac_regs {
	/* per-channel registers */
	struct txx9dmac_cregs	CHAN[TXX9_DMA_MAX_NR_CHANNELS];
	u64	__pad[9];
	u64	MFDR;		/* Memory Fill Data Register */
	TXX9_DMA_REG32(MCR);	/* Master Control Register */
};
struct txx9dmac_regs32 {
	struct txx9dmac_cregs32	CHAN[TXX9_DMA_MAX_NR_CHANNELS];
	u32	__pad[9];
	u32	MFDR;
	u32	MCR;
};

/* bits for MCR */
#define TXX9_DMA_MCR_EIS(ch)	(0x10000000<<(ch))
#define TXX9_DMA_MCR_DIS(ch)	(0x01000000<<(ch))
#define TXX9_DMA_MCR_RSFIF	0x00000080
#define TXX9_DMA_MCR_FIFUM(ch)	(0x00000008<<(ch))
#define TXX9_DMA_MCR_LE		0x00000004
#define TXX9_DMA_MCR_RPRT	0x00000002
#define TXX9_DMA_MCR_MSTEN	0x00000001

/* bits for CCRn */
#define TXX9_DMA_CCR_IMMCHN	0x20000000
#define TXX9_DMA_CCR_USEXFSZ	0x10000000
#define TXX9_DMA_CCR_LE		0x08000000
#define TXX9_DMA_CCR_DBINH	0x04000000
#define TXX9_DMA_CCR_SBINH	0x02000000
#define TXX9_DMA_CCR_CHRST	0x01000000
#define TXX9_DMA_CCR_RVBYTE	0x00800000
#define TXX9_DMA_CCR_ACKPOL	0x00400000
#define TXX9_DMA_CCR_REQPL	0x00200000
#define TXX9_DMA_CCR_EGREQ	0x00100000
#define TXX9_DMA_CCR_CHDN	0x00080000
#define TXX9_DMA_CCR_DNCTL	0x00060000
#define TXX9_DMA_CCR_EXTRQ	0x00010000
#define TXX9_DMA_CCR_INTRQD	0x0000e000
#define TXX9_DMA_CCR_INTENE	0x00001000
#define TXX9_DMA_CCR_INTENC	0x00000800
#define TXX9_DMA_CCR_INTENT	0x00000400
#define TXX9_DMA_CCR_CHNEN	0x00000200
#define TXX9_DMA_CCR_XFACT	0x00000100
#define TXX9_DMA_CCR_SMPCHN	0x00000020
#define TXX9_DMA_CCR_XFSZ(order)	(((order) << 2) & 0x0000001c)
#define TXX9_DMA_CCR_XFSZ_1	TXX9_DMA_CCR_XFSZ(0)
#define TXX9_DMA_CCR_XFSZ_2	TXX9_DMA_CCR_XFSZ(1)
#define TXX9_DMA_CCR_XFSZ_4	TXX9_DMA_CCR_XFSZ(2)
#define TXX9_DMA_CCR_XFSZ_8	TXX9_DMA_CCR_XFSZ(3)
#define TXX9_DMA_CCR_XFSZ_X4	TXX9_DMA_CCR_XFSZ(4)
#define TXX9_DMA_CCR_XFSZ_X8	TXX9_DMA_CCR_XFSZ(5)
#define TXX9_DMA_CCR_XFSZ_X16	TXX9_DMA_CCR_XFSZ(6)
#define TXX9_DMA_CCR_XFSZ_X32	TXX9_DMA_CCR_XFSZ(7)
#define TXX9_DMA_CCR_MEMIO	0x00000002
#define TXX9_DMA_CCR_SNGAD	0x00000001

/* bits for CSRn */
#define TXX9_DMA_CSR_CHNEN	0x00000400
#define TXX9_DMA_CSR_STLXFER	0x00000200
#define TXX9_DMA_CSR_XFACT	0x00000100
#define TXX9_DMA_CSR_ABCHC	0x00000080
#define TXX9_DMA_CSR_NCHNC	0x00000040
#define TXX9_DMA_CSR_NTRNFC	0x00000020
#define TXX9_DMA_CSR_EXTDN	0x00000010
#define TXX9_DMA_CSR_CFERR	0x00000008

Annotation

Implementation Notes