drivers/dpll/zl3073x/core.c
Source file repositories/reference/linux-study-clean/drivers/dpll/zl3073x/core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/dpll/zl3073x/core.c- Extension
.c- Size
- 27081 bytes
- Lines
- 1068
- Domain
- Driver Families
- Bucket
- drivers/dpll
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/bitfield.hlinux/bits.hlinux/dev_printk.hlinux/device.hlinux/export.hlinux/math64.hlinux/module.hlinux/netlink.hlinux/regmap.hlinux/sprintf.hlinux/string_choices.hlinux/unaligned.hnet/devlink.hcore.hdevlink.hdpll.hregs.h
Detected Declarations
function zl3073x_is_volatile_regfunction zl3073x_check_regfunction zl3073x_read_regfunction zl3073x_write_regfunction zl3073x_read_u8function zl3073x_write_u8function zl3073x_read_u16function zl3073x_write_u16function zl3073x_read_u32function zl3073x_write_u32function zl3073x_read_u48function zl3073x_write_u48function zl3073x_poll_zero_u8function zl3073x_mb_opfunction zl3073x_do_hwreg_opfunction zl3073x_read_hwregfunction zl3073x_write_hwregfunction zl3073x_update_hwregfunction zl3073x_write_hwreg_seqfunction zl3073x_dev_state_fetchfunction zl3073x_dev_ref_states_updatefunction zl3073x_dev_chan_states_updatefunction zl3073x_ref_phase_offsets_updatefunction zl3073x_ref_freq_meas_latchfunction zl3073x_ref_freq_meas_updatefunction zl3073x_dev_periodic_workfunction zl3073x_dev_phase_avg_factor_setfunction zl3073x_dev_phase_meas_setupfunction zl3073x_dev_startfunction zl3073x_dev_stopfunction zl3073x_dev_dpll_finifunction zl3073x_devm_dpll_initfunction zl3073x_dev_probe
Annotated Snippet
if (rc) {
dev_err(zldev->dev,
"Failed to fetch input state: %pe\n",
ERR_PTR(rc));
return rc;
}
}
for (i = 0; i < ZL3073X_NUM_SYNTHS; i++) {
rc = zl3073x_synth_state_fetch(zldev, i);
if (rc) {
dev_err(zldev->dev,
"Failed to fetch synth state: %pe\n",
ERR_PTR(rc));
return rc;
}
}
for (i = 0; i < ZL3073X_NUM_OUTS; i++) {
rc = zl3073x_out_state_fetch(zldev, i);
if (rc) {
dev_err(zldev->dev,
"Failed to fetch output state: %pe\n",
ERR_PTR(rc));
return rc;
}
}
for (i = 0; i < zldev->info->num_channels; i++) {
rc = zl3073x_chan_state_fetch(zldev, i);
if (rc) {
dev_err(zldev->dev,
"Failed to fetch channel state: %pe\n",
ERR_PTR(rc));
return rc;
}
}
return rc;
}
static void
zl3073x_dev_ref_states_update(struct zl3073x_dev *zldev)
{
int i, rc;
for (i = 0; i < ZL3073X_NUM_REFS; i++) {
rc = zl3073x_ref_state_update(zldev, i);
if (rc)
dev_warn(zldev->dev,
"Failed to get REF%u status: %pe\n", i,
ERR_PTR(rc));
}
}
static void
zl3073x_dev_chan_states_update(struct zl3073x_dev *zldev)
{
int i, rc;
for (i = 0; i < zldev->info->num_channels; i++) {
rc = zl3073x_chan_state_update(zldev, i);
if (rc)
dev_warn(zldev->dev,
"Failed to get DPLL%u state: %pe\n", i,
ERR_PTR(rc));
}
}
/**
* zl3073x_ref_phase_offsets_update - update reference phase offsets
* @zldev: pointer to zl3073x_dev structure
* @channel: DPLL channel number or -1
*
* The function asks device to update phase offsets latch registers with
* the latest measured values. There are 2 sets of latch registers:
*
* 1) Up to 5 DPLL-to-connected-ref registers that contain phase offset
* values between particular DPLL channel and its *connected* input
* reference.
*
* 2) 10 selected-DPLL-to-all-ref registers that contain phase offset values
* between selected DPLL channel and all input references.
*
* If the caller is interested in 2) then it has to pass DPLL channel number
* in @channel parameter. If it is interested only in 1) then it should pass
* @channel parameter with value of -1.
*
* Return: 0 on success, <0 on error
*/
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/bitfield.h`, `linux/bits.h`, `linux/dev_printk.h`, `linux/device.h`, `linux/export.h`, `linux/math64.h`, `linux/module.h`.
- Detected declarations: `function zl3073x_is_volatile_reg`, `function zl3073x_check_reg`, `function zl3073x_read_reg`, `function zl3073x_write_reg`, `function zl3073x_read_u8`, `function zl3073x_write_u8`, `function zl3073x_read_u16`, `function zl3073x_write_u16`, `function zl3073x_read_u32`, `function zl3073x_write_u32`.
- Atlas domain: Driver Families / drivers/dpll.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.