drivers/edac/skx_common.h

Source file repositories/reference/linux-study-clean/drivers/edac/skx_common.h

File Facts

System
Linux kernel
Corpus path
drivers/edac/skx_common.h
Extension
.h
Size
10349 bytes
Lines
394
Domain
Driver Families
Bucket
drivers/edac
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct reg_rrl {
	/* RRL register parts. */
	int set_num, reg_num;
	enum rrl_source_type sources[NUM_RRL_SET];
	u32 offsets[NUM_RRL_SET][NUM_RRL_REG];
	/* RRL register widths in byte per set. */
	u8 widths[NUM_RRL_REG];
	/* RRL control bits of the first register per set. */
	u32 v_mask;
	u32 uc_mask;
	u32 over_mask;
	u32 en_patspr_mask;
	u32 noover_mask;
	u32 en_mask;

	/* CORRERRCNT register parts. */
	int cecnt_num;
	u32 cecnt_offsets[NUM_CECNT_REG];
	u8 cecnt_widths[NUM_CECNT_REG];
};

/*
 * Each cpu socket contains some pci devices that provide global
 * information, and also some that are local to each of the two
 * memory controllers on the die.
 */
struct skx_dev {
	/* {skx,i10nm}_edac */
	u8 bus[4];
	int seg;
	struct pci_dev *sad_all;
	struct pci_dev *util_all;
	struct pci_dev *uracu;
	struct pci_dev *pcu_cr3;
	u32 mcroute;

	/* imh_edac */
	/* System-view MMIO base physical addresses. */
	u64 mmio_base_h_north;
	u64 mmio_base_h_south;
	int pkg;

	int num_imc;
	struct list_head list;
	struct skx_imc {
		/* i10nm_edac */
		struct pci_dev *mdev;

		/* imh_edac */
		struct device *dev;

		struct mem_ctl_info *mci;
		void __iomem *mbase;
		int chan_mmio_sz;
		int num_channels; /* channels per memory controller */
		int num_dimms; /* dimms per channel */
		bool hbm_mc;
		u8 mc;	/* system wide mc# */
		u8 lmc;	/* socket relative mc# */
		u8 src_id;
		/*
		 * Some server BIOS may hide certain memory controllers, and the
		 * EDAC driver skips those hidden memory controllers. However, the
		 * ADXL still decodes memory error address using physical memory
		 * controller indices. The mapping table is used to convert the
		 * physical indices (reported by ADXL) to the logical indices
		 * (used the EDAC driver) of present memory controllers during the
		 * error handling process.
		 */
		u8 mc_mapping;
		struct skx_channel {
			struct pci_dev	*cdev;
			struct pci_dev	*edev;
			/*
			 * Two groups of RRL control registers per channel to save default RRL
			 * settings of two {sub-,pseudo-}channels in Linux RRL control mode.
			 */
			u32 rrl_ctl[2][NUM_RRL_SET];
			struct skx_dimm {
				u8 close_pg;
				u8 bank_xor_enable;
				u8 fine_grain_bank;
				u8 rowbits;
				u8 colbits;
			} dimms[NUM_DIMMS];
		} chan[NUM_CHANNELS];
	} imc[];
};

struct skx_pvt {

Annotation

Implementation Notes