drivers/fpga/dfl-afu-main.c
Source file repositories/reference/linux-study-clean/drivers/fpga/dfl-afu-main.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/fpga/dfl-afu-main.c- Extension
.c- Size
- 23877 bytes
- Lines
- 987
- Domain
- Driver Families
- Bucket
- drivers/fpga
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/uaccess.hlinux/fpga-dfl.hdfl-afu.h
Detected Declarations
function Unitfunction __afu_port_disablefunction acceleratorfunction port_resetfunction port_get_idfunction id_showfunction ltr_showfunction ltr_storefunction ap1_event_showfunction ap1_event_storefunction ap2_event_showfunction ap2_event_storefunction power_state_showfunction userclk_freqcmd_storefunction userclk_freqcntrcmd_storefunction userclk_freqsts_showfunction userclk_freqcntrsts_showfunction port_hdr_attrs_visiblefunction port_hdr_initfunction port_hdr_ioctlfunction afu_id_showfunction port_afu_attrs_visiblefunction port_afu_initfunction port_stp_initfunction port_uint_ioctlfunction afu_openfunction afu_releasefunction afu_ioctl_check_extensionfunction afu_ioctl_get_infofunction afu_ioctl_get_region_infofunction afu_ioctl_dma_mapfunction afu_ioctl_dma_unmapfunction afu_ioctlfunction dfl_fpga_dev_for_each_featurefunction afu_mmapfunction afu_dev_initfunction afu_dev_destroyfunction port_enable_setfunction afu_probefunction afu_removefunction afu_initfunction afu_exitmodule init afu_init
Annotated Snippet
static const struct file_operations afu_fops = {
.owner = THIS_MODULE,
.open = afu_open,
.release = afu_release,
.unlocked_ioctl = afu_ioctl,
.mmap = afu_mmap,
};
static int afu_dev_init(struct platform_device *pdev)
{
struct dfl_feature_dev_data *fdata = to_dfl_feature_dev_data(&pdev->dev);
struct dfl_afu *afu;
afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL);
if (!afu)
return -ENOMEM;
mutex_lock(&fdata->lock);
dfl_fpga_fdata_set_private(fdata, afu);
afu_mmio_region_init(fdata);
afu_dma_region_init(fdata);
mutex_unlock(&fdata->lock);
return 0;
}
static int afu_dev_destroy(struct platform_device *pdev)
{
struct dfl_feature_dev_data *fdata = to_dfl_feature_dev_data(&pdev->dev);
mutex_lock(&fdata->lock);
afu_mmio_region_destroy(fdata);
afu_dma_region_destroy(fdata);
dfl_fpga_fdata_set_private(fdata, NULL);
mutex_unlock(&fdata->lock);
return 0;
}
static int port_enable_set(struct dfl_feature_dev_data *fdata, bool enable)
{
int ret;
mutex_lock(&fdata->lock);
if (enable)
ret = __afu_port_enable(fdata);
else
ret = __afu_port_disable(fdata);
mutex_unlock(&fdata->lock);
return ret;
}
static struct dfl_fpga_port_ops afu_port_ops = {
.name = DFL_FPGA_FEATURE_DEV_PORT,
.owner = THIS_MODULE,
.get_id = port_get_id,
.enable_set = port_enable_set,
};
static int afu_probe(struct platform_device *pdev)
{
int ret;
dev_dbg(&pdev->dev, "%s\n", __func__);
ret = afu_dev_init(pdev);
if (ret)
goto exit;
ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs);
if (ret)
goto dev_destroy;
ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE);
if (ret) {
dfl_fpga_dev_feature_uinit(pdev);
goto dev_destroy;
}
return 0;
dev_destroy:
afu_dev_destroy(pdev);
exit:
return ret;
}
static void afu_remove(struct platform_device *pdev)
{
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/uaccess.h`, `linux/fpga-dfl.h`, `dfl-afu.h`.
- Detected declarations: `function Unit`, `function __afu_port_disable`, `function accelerator`, `function port_reset`, `function port_get_id`, `function id_show`, `function ltr_show`, `function ltr_store`, `function ap1_event_show`, `function ap1_event_store`.
- Atlas domain: Driver Families / drivers/fpga.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.