drivers/fpga/dfl.c
Source file repositories/reference/linux-study-clean/drivers/fpga/dfl.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/fpga/dfl.c- Extension
.c- Size
- 49813 bytes
- Lines
- 2026
- Domain
- Driver Families
- Bucket
- drivers/fpga
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dfl.hlinux/fpga-dfl.hlinux/module.hlinux/overflow.hlinux/uaccess.hdfl.h
Detected Declarations
struct dfl_dev_infostruct dfl_chardev_infostruct build_feature_devs_infostruct dfl_feature_infoenum dfl_fpga_devt_typefunction dfl_ids_initfunction dfl_ids_destroyfunction dfl_id_allocfunction dfl_id_freefunction dfh_id_to_typefunction list_for_each_entryfunction dfl_fpga_port_ops_putfunction dfl_fpga_port_ops_addfunction dfl_fpga_port_ops_delfunction dfl_fpga_check_port_idfunction dfl_match_one_devicefunction dfl_bus_matchfunction dfl_bus_probefunction dfl_bus_removefunction dfl_bus_ueventfunction type_showfunction feature_id_showfunction release_dfl_devfunction dfl_dev_addfunction dfl_devs_removefunction dfl_fpga_dev_for_each_featurefunction dfl_devs_addfunction dfl_fpga_dev_for_each_featurefunction __dfl_driver_registerfunction dfl_driver_unregisterfunction dfl_fpga_dev_feature_uinitfunction dfl_fpga_dev_for_each_featurefunction dfl_feature_instance_initfunction dfl_feature_drv_matchfunction dfl_fpga_dev_feature_initfunction dfl_chardev_uinitfunction dfl_chardev_initfunction dfl_get_devtfunction dfl_fpga_dev_ops_registerfunction dfl_fpga_dev_ops_unregisterfunction dfl_fpga_cdev_add_port_datafunction dfl_id_free_actionfunction binfo_create_feature_dev_datafunction functionsfunction feature_dev_registerfunction feature_dev_unregisterfunction build_info_commit_devfunction build_info_free
Annotated Snippet
static int dfl_bus_match(struct device *dev, const struct device_driver *drv)
{
struct dfl_device *ddev = to_dfl_dev(dev);
const struct dfl_driver *ddrv = to_dfl_drv(drv);
const struct dfl_device_id *id_entry;
id_entry = ddrv->id_table;
if (id_entry) {
while (id_entry->feature_id) {
if (dfl_match_one_device(id_entry, ddev)) {
ddev->id_entry = id_entry;
return 1;
}
id_entry++;
}
}
return 0;
}
static int dfl_bus_probe(struct device *dev)
{
struct dfl_driver *ddrv = to_dfl_drv(dev->driver);
struct dfl_device *ddev = to_dfl_dev(dev);
return ddrv->probe(ddev);
}
static void dfl_bus_remove(struct device *dev)
{
struct dfl_driver *ddrv = to_dfl_drv(dev->driver);
struct dfl_device *ddev = to_dfl_dev(dev);
if (ddrv->remove)
ddrv->remove(ddev);
}
static int dfl_bus_uevent(const struct device *dev, struct kobj_uevent_env *env)
{
const struct dfl_device *ddev = to_dfl_dev(dev);
return add_uevent_var(env, "MODALIAS=dfl:t%04Xf%04X",
ddev->type, ddev->feature_id);
}
static ssize_t
type_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dfl_device *ddev = to_dfl_dev(dev);
return sprintf(buf, "0x%x\n", ddev->type);
}
static DEVICE_ATTR_RO(type);
static ssize_t
feature_id_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct dfl_device *ddev = to_dfl_dev(dev);
return sprintf(buf, "0x%x\n", ddev->feature_id);
}
static DEVICE_ATTR_RO(feature_id);
static struct attribute *dfl_dev_attrs[] = {
&dev_attr_type.attr,
&dev_attr_feature_id.attr,
NULL,
};
ATTRIBUTE_GROUPS(dfl_dev);
static const struct bus_type dfl_bus_type = {
.name = "dfl",
.match = dfl_bus_match,
.probe = dfl_bus_probe,
.remove = dfl_bus_remove,
.uevent = dfl_bus_uevent,
.dev_groups = dfl_dev_groups,
};
static void release_dfl_dev(struct device *dev)
{
struct dfl_device *ddev = to_dfl_dev(dev);
if (ddev->mmio_res.parent)
release_resource(&ddev->mmio_res);
kfree(ddev->params);
ida_free(&dfl_device_ida, ddev->id);
kfree(ddev->irqs);
Annotation
- Immediate include surface: `linux/dfl.h`, `linux/fpga-dfl.h`, `linux/module.h`, `linux/overflow.h`, `linux/uaccess.h`, `dfl.h`.
- Detected declarations: `struct dfl_dev_info`, `struct dfl_chardev_info`, `struct build_feature_devs_info`, `struct dfl_feature_info`, `enum dfl_fpga_devt_type`, `function dfl_ids_init`, `function dfl_ids_destroy`, `function dfl_id_alloc`, `function dfl_id_free`, `function dfh_id_to_type`.
- Atlas domain: Driver Families / drivers/fpga.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.